Gate Structure and Impurity Layout Against PMIC Parasitic BJT Overcurrent
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Solution Overview
Problem
During the operation of a power management integrated circuit (PMIC), overcurrent occurs due to parasitic operation of a bipolar junction transistor (BJT) triggered by activation of a diode and ripple, leading to potential burning of circuit patterns.
Innovation Solution
A semiconductor device is designed with a gate structure and impurity regions, including n-type and p-type impurity regions, and a wiring structure with wirings at multiple levels. The fourth impurity region is doped with p-type impurities and is positioned such that it does not overlap with the uppermost wiring level, reducing current flow and preventing circuit pattern burning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PMIC circuit is operated, then normal power management function is achieved, but overcurrent occurs due to parasitic BJT operation causing circuit pattern burning
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the fourth impurity region (p-type) and gate structure to counteract the parasitic BJT operation before overcurrent can damage the circuit. The p-type fourth impurity region is positioned to preemptively block the harmful current path that would otherwise flow through the n-type first impurity region, preventing the burning of circuit patterns before it occurs.
Solution Approach 2:
The patent applies local quality by creating a specific p-type doped region (fourth impurity region) at a precise location adjacent to the n-type first impurity region, while maintaining different doping types in different areas. This localized p-type region selectively blocks overcurrent in the critical area without affecting the normal operation of other circuit regions, achieving spatially differentiated functionality.
2Reliability
If the fourth impurity region is positioned to block overcurrent, then circuit pattern burning is prevented, but device structure complexity increases
Solution Approach 1:
The patent merges the protective function into the existing transistor structure by integrating the fourth impurity region as part of the transistor's impurity region configuration. Rather than adding a separate protective component, the p-type fourth impurity region is combined with the n-type first impurity region to form an integrated structure that simultaneously achieves normal transistor operation and overcurrent protection.
Solution Approach 2:
The fourth impurity region serves multiple functions: it maintains normal transistor operation during standard power management tasks while simultaneously providing overcurrent protection by blocking parasitic BJT operation. This multi-functional element eliminates the need for separate protection circuits, reducing overall device complexity despite the added doping region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device effectively reduces the risk of overcurrent and circuit pattern burning by locally reducing current flow and increasing the on-current breakdown voltage (ON BV), thereby enhancing the reliability of the PMIC.
Implementation Method 1
first and second impurity regions are each doped with n-type impurities, a third impurity region is doped with p-type impurities, a fourth impurity region is doped with p-type impurities
Data Source
AI summary
A semiconductor device includes a gate structure disposed on a substrate and extending along a first direction that is substantially parallel to an upper surface of the substrate, first and second impurity regions disposed on portions of the substrate at opposite sides of the gate structure along a second direction that is substantially parallel to the upper surface of the substrate, the first and second impurity regions being substantially perpendicular to each other, wherein the first and second impurity regions are each doped with n-type impurities, a third impurity region disposed on a portion of the substrate adjacent to the first impurity region along the second direction, wherein the third impurity region is doped with p-type impurities, a fourth impurity region disposed on a portion of the substrate adjacent to the first impurity region along the first direction, wherein the fourth impurity region is connected to the third impurity region and is doped with p-type impurities and a wiring structure disposed on the gate structure, wherein the wiring structure includes wirings that are disposed on a plurality of different levels. The fourth impurity region does not overlap a first one of the wirings along a vertical direction that is substantially perpendicular to the upper surface of the substrate. The first one of the wirings is disposed at an uppermost level among the plurality of different levels.