Gate Inner Spacer Structure for Source/Drain Contact Alignment
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Solution Overview
Problem
Existing semiconductor devices face challenges in forming lower source/drain and gate contacts without damaging the gate pattern, controlling lateral growth of source/drain patterns, reducing parasitic capacitance, simplifying the cutting process of the gate pattern, and minimizing variation in threshold voltage (Vt).
Innovation Solution
A semiconductor device design that includes a gate inner spacer with overlapping and non-overlapping portions, a partition wall pattern, and self-alignment of contacts, which prevents gate pattern damage, controls lateral growth, reduces parasitic capacitance, and minimizes threshold voltage variation by protecting the work function metal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a lower source/drain contact is formed without additional structures, then manufacturing complexity is reduced, but gate pattern damage may occur
Solution Approach 1:
A protective layer is formed over the gate pattern before forming the lower source/drain contact. This preliminary protective action prevents gate pattern damage during subsequent contact formation processes, eliminating the need for additional place holder structures while maintaining gate integrity.
Solution Approach 2:
The protective layer acts as an intermediary element between the gate pattern and the lower source/drain contact formation process. This intermediate layer protects the gate pattern from damage during contact formation without requiring additional structural components.
2Manufacturing precision
If lateral growth of source/drain patterns is controlled, then device precision is improved, but additional control structures increase device complexity
Solution Approach 1:
The method utilizes self-aligned formation of the protective layer and selective area growth control to achieve precise lateral dimensional control of source/drain patterns. The process self-regulates through the protective layer configuration and etch selectivity, eliminating the need for additional lateral control structures.
Solution Approach 2:
The invention controls lateral growth by adjusting process parameters including etch selectivity ratios, protective layer thickness, and deposition conditions. These parameter changes enable precise dimensional control without adding structural complexity.
3Reliability
If the gate pattern is protected from damage, then reliability is improved, but additional protective structures increase device complexity
Solution Approach 1:
The protective layer serves multiple functions simultaneously: it protects the gate pattern from damage during contact formation, defines the lateral boundaries of source/drain patterns, and acts as an etch stop layer. This multi-functionality eliminates the need for separate protective structures.
Solution Approach 2:
The protective layer is formed and configured to automatically provide gate protection through the manufacturing process itself, without requiring additional dedicated protective structures. The process utilizes the protective layer's inherent properties to safeguard the gate pattern.
4Reliability
If parasitic capacitance is reduced by preventing gate pattern recession, then device performance is improved, but additional control measures increase device complexity
Solution Approach 1:
The protective layer is formed preliminarily before gate recess processes to prevent gate pattern recession. This preliminary protection maintains the original gate height, reducing parasitic capacitance without requiring additional gate height control structures.
Solution Approach 2:
The protective layer acts as an intermediary that prevents direct contact between processing tools and the gate pattern during recess operations. This intermediate protection maintains gate height integrity and reduces parasitic capacitance without adding structural complexity.
Data Source
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AI summary
A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.