Gate-Insulated Schottky Diode Cell Layout for Lower Conduction Loss
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Solution Overview
Problem
The existing semiconductor device structure with separate Schottky cells and p-n diode cells leads to scattered current paths, resulting in inadequate increase in forward current with respect to forward voltage, thereby increasing conduction loss in Schottky barrier diodes.
Innovation Solution
A semiconductor device is designed with a unit cell that includes a diode region of a first conductivity type, a well region of a second conductivity type, and a first conductivity type region, where a gate electrode layer faces the well and first conductivity type region through a gate insulating layer, forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Schottky cell and p-n diode cell are formed separately, then device structure is simplified and manufacturable, but current paths become scattered and conduction loss increases
Solution Approach 1:
The patent combines the Schottky cell and p-n diode cell into a single integrated cell structure. The Schottky barrier diode and the insulating gate type transistor share common regions (diode region, well region, first conductivity type region) within the same cell, eliminating the need for separate cell structures. This merging approach consolidates current paths and reduces conduction loss while maintaining ease of manufacture through a unified fabrication process.
2Ease of manufacture
If separate cell structures are used, then manufacturing process is easier, but forward current increase with respect to forward voltage is insufficient
Solution Approach 1:
By merging the Schottky cell and p-n diode cell into one integrated structure, the patent creates shared current paths that enhance the forward current increase rate with respect to forward voltage. The common diode region and conductivity type regions enable more efficient current flow compared to separate structures, improving productivity without complicating the manufacturing process.
3Device complexity
If current paths are scattered, then device structure is simpler, but conduction loss increases
Solution Approach 1:
The integrated cell structure merges the functional regions of the Schottky barrier diode and insulating gate type transistor, creating concentrated and efficient current paths. The shared diode region, well region, and conductivity type regions eliminate the scattering effect of separate structures, reducing conduction loss while maintaining manageable device complexity through a systematic layout.
4Loss of energy
If Schottky barrier diode conduction loss is reduced, then energy efficiency improves, but requires more complex current path configuration
Solution Approach 1:
The patent achieves reduced conduction loss through a merging approach that integrates the Schottky barrier diode and insulating gate type transistor in a single cell. This configuration naturally concentrates current paths without requiring additional complex routing or separate structures, as the shared regions (diode region, well region, conductivity type regions) inherently guide current flow efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses the scattering of current paths for Schottky barrier diodes and transistors, allowing for a greater increase in forward current with respect to forward voltage, thereby reducing conduction loss in Schottky barrier diodes.
Implementation Method 1
a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer... forming a Schottky junction with the diode region
Implementation Method 2
a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a first surface and a second surface, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first surface electrode covering the diode region and the first conductivity type region on the first surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.