Gate Insulating Film Thickness Control in Semiconductor Fabrication
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Solution Overview
Problem
In semiconductor device fabrication, forming gate insulating films with different thicknesses is challenging due to issues with wet etching, which can lead to device-isolation insulating film etching and electric field concentration, hindering the miniaturization of semiconductor devices.
Innovation Solution
A method involving the formation of first to third gate insulating films with decreasing thicknesses on a semiconductor substrate, using resist patterns and reticles designed to minimize etching overlap and prevent graphic interference, allowing for precise control of etching and reducing the width of the device-isolation insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching is performed multiple times to form gate insulating films of different thicknesses, then the desired thickness variation is achieved, but the device-isolation insulating film is etched and electric field concentrates at the etched portions
Solution Approach 1:
The patent applies preliminary action by forming a protective film on the device-isolation insulating film before the wet etching process. This protective film prevents the etchant from attacking the device-isolation insulating film during the gate insulating film thickness differentiation process, thereby eliminating the harmful etching effects while still achieving the desired thickness variation.
Solution Approach 2:
The protective film acts as an intermediary layer between the wet etchant and the device-isolation insulating film. It selectively protects the device-isolation regions while allowing the etchant to access and thin the gate insulating films in the active regions, thus mediating the etching process to achieve precise thickness control without damaging critical structures.
2Length of moving object
If the width of device-isolation insulating film is reduced to enable miniaturization, then device density increases, but it becomes more difficult to prevent etching overlap and maintain thickness uniformity
Solution Approach 1:
The protective film is formed in advance on the device-isolation insulating film before the wet etching process. This preliminary protective action ensures that even when the device-isolation insulating film width is reduced for miniaturization, the etchant cannot penetrate and cause overlapping etching or damage, thereby maintaining manufacturing precision despite the reduced dimensions.
3Speed
If gate insulating films are formed to be thin to improve operation speed, then driving ability increases, but leakage currents between substrate and gates increase
Solution Approach 1:
The patent applies local quality by creating different gate insulating film thicknesses in different regions: thin gate insulating films in the core unit active regions for high-speed operation, and thick gate insulating films in the input/output unit active regions for low leakage current. This spatial differentiation of thickness allows each region to have the optimal characteristics for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization of semiconductor devices by preventing etching of gate insulating films in regions other than the target active regions, reducing leakage currents, and enhancing the design efficiency of high-speed transistors without compromising the thickness uniformity of gate insulating films.
Implementation Method 1
removing the first gate insulating film of the second active region through the first resist opening portion by wet etching
Implementation Method 2
removing the first gate insulating film of the third active region through the second resist opening portion by wet etching
Data Source
AI summary
The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region.