Gate Insulating Layer Reduces Parasitic Capacitance in Power FETs
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Solution Overview
Problem
The parasitic capacitance between the gate metal and the overlying field plate in power FET devices degrades device performance by reducing gain and unity current gain frequency (fT), and increasing dielectric thickness to mitigate this affects the efficacy of the field plate.
Innovation Solution
Incorporating an insulating material layer, such as silicon dioxide or silicon nitride, between the gate metal and the field plate to reduce parasitic capacitance without compromising the field plate's effectiveness, achieved by converting the top portion of the gate metal stack into an insulating layer through oxidation or nitridation, or depositing an insulating material as part of the gate metal stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If dielectric thickness between gate and field plate is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but field plate efficacy is compromised
Solution Approach 1:
The patent applies local quality by creating a non-uniform dielectric structure where the gate dielectric layer has varying thickness - thicker in regions where parasitic capacitance reduction is needed and thinner where field plate efficacy must be maintained. This localized variation in dielectric thickness allows simultaneous optimization of both contradictory requirements.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a single-dimensional (uniform thickness) dielectric structure to a multi-dimensional structure with spatially varying thickness. The dielectric layer thickness becomes a function of position, allowing different regions to serve different functions - reducing parasitic capacitance in some areas while maintaining field plate coupling in others.
2Strength
If field plate is placed in proximity to gate to increase breakdown voltage, then breakdown voltage is increased, but parasitic capacitance increases degrading gain and fT
Solution Approach 1:
The patent maintains the field plate's proximity to the gate for breakdown voltage enhancement while applying local quality through spatially varying dielectric thickness. The thinner dielectric regions preserve strong electric field coupling for voltage breakdown protection, while thicker dielectric regions in specific locations reduce parasitic capacitance between gate and field plate.
Solution Approach 2:
The patent segments the dielectric space between gate and field plate into regions of different thicknesses. This segmentation allows the structure to simultaneously provide strong coupling where needed for breakdown voltage and reduced capacitance where needed for frequency performance, resolving the contradiction through spatial division of functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance by at least 5-10% while maintaining capacitive coupling between the field plate and the channel, thereby enhancing the device's gain and fT performance.
Implementation Method 1
converting the top portion of the gate metal stack into an insulating layer through oxidation or nitridation
Implementation Method 2
converting the top portion of the gate metal stack into an insulating layer through oxidation or nitridation
Data Source
AI summary
A transistor device includes a semiconductor substrate and a gate structure formed at the upper surface of the substrate. The gate structure includes a metal gate electrode and a gate insulating layer overlying the metal gate electrode, where edges of the gate insulating layer correspond to edges of the metal gate electrode. The transistor device also includes a first dielectric layer formed over the gate structure, and a first interconnect metal layer formed over the first dielectric layer. A portion of the first interconnect metal layer forms a field plate proximate to the gate structure, and a portion of the gate insulating layer and a portion of the first dielectric layer are present between the gate electrode and the field plate.