Gate Insulating Layer Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) leads to deterioration in operational properties due to issues like interface traps, border traps, and fixed charges in the silicon nitride inner spacer, affecting the electrical and reliability characteristics of semiconductor devices.
Innovation Solution
A semiconductor device with a gate insulating layer having a thicker inner portion between the inner electrode and the source/drain pattern and a thinner outer portion, replacing the traditional inner spacer, and using selective epitaxial growth to form source/drain patterns with a SiGe or SiGeC layer that protrudes towards the inner gate insulating layer, enhancing the device's electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for small pattern size, then device size is reduced, but operational properties deteriorate due to interface trap, border trap, and fixed charge issues
Solution Approach 1:
The patent transitions from a planar MOSFET structure to a three-dimensional FinFET structure by introducing vertical fins that extend from the substrate. This dimensional change increases the effective channel area and improves gate control without increasing the planar footprint, thereby maintaining small device size while improving operational properties through better electrostatic control and reduced short-channel effects
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and selectively doped semiconductor regions with different crystalline orientations. These composite structures enable improved carrier mobility, better threshold voltage control, and reduced interface traps, thereby enhancing reliability while maintaining scaled dimensions
2Strength
If inner spacer is formed using silicon nitride layer, then structural support is provided, but interface trap, border trap, and fixed charge issues arise
Solution Approach 1:
The patent removes the silicon nitride inner spacer layer entirely and replaces it with alternative structures such as mandrel-based spacers or directly formed gate structures. This extraction eliminates the source of interface traps and fixed charges associated with silicon nitride while maintaining necessary structural support through differently configured spacer materials or geometric designs
Solution Approach 2:
The patent introduces intermediary layers such as thin oxide barriers or interface engineering layers between the gate structure and semiconductor channel. These intermediary layers provide the necessary structural support and spacing functions previously performed by the silicon nitride inner spacer, while simultaneously reducing interface traps and improving electrical characteristics through optimized material interfaces
3Ease of manufacture
If gate insulating layer has uniform thickness, then fabrication is simplified, but leakage current increases and electrical performance deteriorates
Solution Approach 1:
The patent implements a gate insulating layer with non-uniform thickness where the dielectric thickness varies spatially across the gate structure. Specifically, the insulating layer is thinner at the center of the gate and thicker at the edges, or vice versa depending on the specific embodiment. This local variation optimizes electrical performance by reducing leakage paths and improving field distribution, while the overall structure remains compatible with standard fabrication processes through selective etching or deposition techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical and reliability characteristics of the semiconductor device by reducing leakage currents and preventing charge trapping, while also simplifying the fabrication process by omitting the inner spacer formation steps.
Implementation Method 1
preventing charge trapping
Implementation Method 2
reducing leakage currents
Implementation Method 3
selective epitaxial growth to form source/drain patterns with a SiGe or SiGeC layer
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including, an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns.