Gate Insulating Layer Configuration for Semiconductor Device Resistance
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Solution Overview
Problem
As semiconductor devices are miniaturized, the reduction in gate electrode sizes leads to increased gate resistance due to narrower gate trenches and smaller spaces filled with gate electrodes, which affects the performance and refresh speed of memory devices.
Innovation Solution
The semiconductor device incorporates an upper and lower gate insulating layer configuration within the gate trench, where the inner diameter of the upper end of the lower gate insulating layer is greater than the inner diameter of the lower end of the upper gate insulating layer, ensuring a wider space for the gate electrode and reducing gate resistance. This configuration includes a first and second gate barrier layer to enhance adhesion and prevent material diffusion, along with a gate buried portion and capping layer to manage gate-induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If gate electrode size is reduced to miniaturize semiconductor devices, then device compactness is improved, but gate resistance increases
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional gate-all-around (GAA) structure where the gate electrode completely surrounds the channel in multiple dimensions. This vertical and lateral wrapping of the gate electrode increases the effective gate area without increasing the device footprint, thereby reducing gate resistance while maintaining compact device size.
Solution Approach 2:
The patent employs a composite gate structure consisting of multiple materials including the gate electrode (e.g., polysilicon, metal), gate insulating layers (e.g., silicon oxide, silicon nitride), and gate barrier layers. This composite structure optimizes electrical properties by combining materials with different characteristics, reducing gate resistance through careful material selection and layer configuration while maintaining device miniaturization.
2Volume of moving object
If gate trench size is reduced to miniaturize devices, then device compactness is improved, but gate-induced drain leakage increases
Solution Approach 1:
The patent segments the gate structure into multiple functional layers including the gate electrode, gate insulating layers, and gate barrier layers. This segmentation allows each layer to perform its specific function: the gate insulating layers provide electrical isolation to prevent leakage, while the gate barrier layers control material diffusion, thereby reducing gate-induced drain leakage while maintaining compact device dimensions.
Solution Approach 2:
The patent introduces gate insulating layers and gate barrier layers as intermediary structures between the gate electrode and the channel/drain regions. These intermediary layers act as barriers that prevent direct interaction and leakage paths, effectively reducing gate-induced drain leakage while allowing the device to maintain miniaturized dimensions.
Data Source
AI summary
A semiconductor device includes gate trench, an upper gate insulating layer on an inner surface of an upper region of the gate trench, a lower gate insulating layer on an inner surface and a lower surface of a lower region of the gate trench and connected to the upper gate insulating layer, a first gate barrier layer on an inner side of the lower gate insulating layer, a gate electrode on an inner side of the first gate barrier layer and configured to fill the lower region of the gate trench, and a gate buried portion on the gate electrode. A diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.