Gate Insulating Layer Structure for Stable TFT Display Panels
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Solution Overview
Problem
The existing gate insulating layers in display panels are prone to electron transitions due to environmental effects like strong light, leading to voltage biases and instability in thin film transistors, which affects the display performance.
Innovation Solution
Incorporating an electron suppressing layer with a nitrogen-to-silicon ratio greater than 0.95 and an electron blocking layer in the gate insulating layer, which reduces the likelihood of gate electrons jumping into the insulating layer, thereby enhancing the optical band gap and stability of the thin film transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate insulating layer is used, then the manufacturing process is simple, but gate electrons easily jump into the gate insulating layer under strong light environments, affecting the on-state voltage and display effect
Solution Approach 1:
The gate insulating layer is divided into multiple sub-layers: a first gate insulating layer (SiN layer) directly on the gate, a second gate insulating layer (SiOx layer) on top of the first layer, and optionally a third gate insulating layer (SiN layer) on top of the second layer. This segmentation allows each layer to perform specific functions in preventing electron transitions while maintaining overall structural stability.
Solution Approach 2:
The patent uses composite material structure by combining different insulating materials (silicon nitride and silicon oxide) with different properties. The SiN layers provide high electron barrier properties, while the SiOx layer provides good insulation and interface quality. This composite approach creates a multi-functional gate insulating system that effectively blocks electron transitions under strong light conditions.
2Reliability
If the gate insulating layer is made thicker to prevent electron transitions, then electron blocking capability improves, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
Instead of using a single thick gate insulating layer that would be difficult to manufacture uniformly, the patent segments the insulation function into multiple thinner layers. Each layer can be deposited with standard thickness control, making the manufacturing process more manageable while achieving the same or better electron blocking performance through the combined effect of multiple interfaces.
Solution Approach 2:
The patent optimizes the thickness and material composition parameters of each gate insulating layer to achieve effective electron blocking. By carefully controlling the thickness of each SiN and SiOx layer, the design achieves high electron barrier capability while maintaining compatibility with existing manufacturing processes and equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces electron transitions, improves the stability of thin film transistors, and enhances the display effect by maintaining the on-state voltage and overall performance of the display panel.
Implementation Method 1
enhancing the optical band gap and stability of the thin film transistors
Data Source
AI summary
Display panels, methods of manufacturing a display panel, and display devices are provided. The display panel includes a substrate and a thin film transistor layer disposed on the substrate. The thin film transistor layer includes a gate, a gate insulating layer and an active layer; the gate is disposed on the substrate; the gate insulating layer is disposed on the substrate and covers the gate; and the active layer is disposed on a side of the gate insulating layer away from the gate. The gate insulating layer includes an electron suppressing layer at least covering a side of the gate away from the substrate and an electron blocking layer disposed on a side of the electron suppressing layer away from the gate, and a ratio of nitrogen to silicon in the electron suppressing layer is greater than 0.95.