Gate Insulation Layer Stack for Leakage-Resistant Semiconductor Scaling
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Solution Overview
Problem
As the degree of integration of semiconductor devices increases, the reduced gate area of transistors leads to decreased gate insulation layer capacitance, potentially causing leakage current and deteriorating transistor performance.
Innovation Solution
A method for manufacturing a semiconductor device that includes forming a first insulation layer over a second region of a semiconductor substrate, a capping layer to cover the first insulation layer, a charge transfer layer over the first region, and a second insulation layer over the charge transfer layer, thereby enhancing the reliability of the gate insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate area of transistors is reduced to increase degree of integration, then device integration density improves, but gate insulation layer capacitance decreases leading to leakage current and performance deterioration
Solution Approach 1:
The patent applies local quality by forming a charge transfer layer specifically over the first region (gate region) while leaving the second region (source/drain region) with standard insulation. This localized modification provides enhanced capacitance and reduced leakage current precisely where needed in the gate area, without affecting other regions of the transistor structure.
Solution Approach 2:
The patent uses composite materials by combining the first insulation layer (formed by radical oxidation) with the charge transfer layer (formed by atomic layer deposition). This composite structure integrates the high-quality oxide layer from radical oxidation with the precisely controllable ALD layer, creating a multi-layer gate insulation system that achieves both high capacitance and low leakage current.
2Productivity
If the thickness of gate insulation layer is reduced to maintain capacitance, then device scaling improves, but leakage current increases causing performance deterioration
Solution Approach 1:
The patent employs composite materials by creating a multi-layer gate insulation structure consisting of a first insulation layer and a charge transfer layer. This composite structure allows for reduced overall thickness while maintaining adequate capacitance through the combined dielectric properties of multiple layers, thereby reducing leakage current without sacrificing device scaling.
Solution Approach 2:
The patent applies parameter changes by modifying the dielectric properties of the gate insulation layer through the addition of a charge transfer layer with specific charge characteristics. This changes the electrical parameters (capacitance and leakage current) of the gate insulation system, enabling thinner structures to achieve the same or better performance than thicker conventional layers.
3Reliability
If a charge transfer layer is formed to improve gate insulation reliability, then leakage current reduces, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the first insulation layer using radical oxidation before forming the charge transfer layer through atomic layer deposition. This sequence ensures that the substrate is properly prepared and cleaned, providing an optimal foundation for the charge transfer layer formation, which in turn ensures high-quality gate insulation with reduced leakage current.
Solution Approach 2:
The patent uses the first insulation layer formed by radical oxidation as an intermediary between the substrate and the charge transfer layer. This intermediate layer serves multiple functions: it provides a clean, oxide-covered surface for subsequent ALD processing, acts as a buffer layer, and contributes to the overall dielectric properties, thereby facilitating the formation of a reliable gate insulation structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method improves the reliability of the gate insulation layer, reducing the likelihood of leakage current and enhancing the overall performance and reliability of semiconductor devices.
Implementation Method 1
the first insulation layer may be formed using at least one of a radical oxidation process, atomic layer deposition (ALD), chemical vapor deposition (CVD), or a wet chemical process
Implementation Method 2
the first insulation layer may be formed using at least one of a radical oxidation process, atomic layer deposition (ALD), chemical vapor deposition (CVD), or a wet chemical process
Implementation Method 3
forming a charge transfer layer over the first region... carriers moving inside the charge transfer layer may be holes
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first insulation layer over a second region of a semiconductor substrate including first and second regions, forming a capping layer to cover the first insulation layer located over the second region, forming a charge transfer layer over the first region, and forming a second insulation layer over the charge transfer layer located over the first region.