Gate Insulation Test Structure for Plasma Damage Detection
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in accurately and reliably testing gate insulation of transistors due to plasma-induced charging, which can damage the gate oxide and lead to shifts in transistor parameters over time, potentially causing product failure.
Innovation Solution
A semiconductor device with a test structure comprising a conductive structure connected to the gate or doping region of a transistor through a wiring layer, allowing for the application of predefined currents or voltages and measurement of corresponding voltages or currents, thereby avoiding plasma-induced charging and enabling accurate determination of gate insulation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma processes are used for manufacturing, then productivity and manufacturing capability are improved, but plasma-induced charging damages the gate oxide and reduces reliability
Solution Approach 1:
The patent applies preliminary action by performing a gate insulation test during the manufacturing process, before the plasma-induced charging damage can affect product reliability. The test structure includes a conductive structure connected to the gate through a wiring layer, allowing early detection of gate oxide quality issues before plasma processing occurs in subsequent manufacturing steps.
2Device complexity
If conventional test structures are used, then device complexity is reduced, but measurement precision and reliability of gate insulation testing are insufficient
Solution Approach 1:
The patent applies segmentation by separating the test function from the product structure. A dedicated test structure with conductive structures in wiring layers is created specifically for gate insulation testing, allowing accurate measurement without affecting the main product device. This segmented approach enables precise testing while keeping the product design clean.
Solution Approach 2:
The patent uses an intermediary approach by introducing a conductive structure through a wiring layer that connects to the gate without being part of the main product circuitry. This intermediary test structure allows measurement of gate insulation properties without directly interfering with the product operation, providing accurate testing while maintaining product integrity.
3Ease of manufacture
If simple test structures are used, then ease of manufacture is improved, but the ability to accurately detect plasma-induced damage is reduced
Solution Approach 1:
The patent merges the test structure fabrication with the existing product manufacturing process. The conductive structures are formed using the same wiring layer processes already established for the product, allowing the test structure to be manufactured simultaneously with the product without adding separate fabrication steps. This merging enables easy manufacture while maintaining the capability to detect plasma-induced damage through the dedicated test structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more accurate and reliable testing of gate insulation by simulating operational conditions and measuring leakage currents, ensuring consistent stress on the gate oxide, thus identifying potential damage and improving transistor reliability.
Implementation Method 1
The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer
Implementation Method 2
testing a gate insulation of a transistor structure... measuring a first voltage between the first test pad and the second test pad... during applying the predefined current or a first current
Data Source
AI summary
A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.