Gate Insulator Stray Capacitance Reduction via Local Dielectric Quality
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Solution Overview
Problem
Existing methods for fabricating field-effect transistors with small dimensions face challenges in reducing stray capacitances between the gate and source/drain contacts, particularly due to enhanced capacitances caused by high-permittivity gate insulators, which are not optimal for large-scale production and lead to dispersion issues.
Innovation Solution
A method involving the formation of low-permittivity spacers on a high-permittivity gate insulator, where a conformal deposition of a high-permittivity dielectric layer is followed by selective etching to create a thick enough layer under sacrificial spacers, and then low-permittivity spacers are formed on either side of the gate metal to reduce stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If high-permittivity gate insulator (Hk) is used to reduce gate leakage current, then power consumption is reduced, but stray capacitance between gate and source/drain contacts increases
Solution Approach 1:
The patent applies different dielectric materials with different permittivity values in different spatial locations. Specifically, Hk material is used in the region directly under the gate electrode where low leakage is critical, while Lk material is used in the lateral regions extending toward source and drain contacts where stray capacitance is the concern. This local differentiation allows simultaneous optimization of both power consumption and stray capacitance.
Solution Approach 2:
The gate insulator structure employs a composite configuration combining two dielectric materials: a first gate dielectric layer made of Hk material and a second gate dielectric layer made of Lk material. The Hk layer provides low leakage current, while the Lk layer reduces stray capacitance. This composite approach leverages the complementary strengths of both materials to resolve the contradiction between power consumption and stray capacitance.
2Productivity
If gate length is reduced to increase transistor density, then productivity is improved, but stray capacitance increases due to reduced distances between gate and contacts
Solution Approach 1:
The patent addresses the stray capacitance issue in scaled devices by implementing spatially varying dielectric properties. The Lk material is specifically positioned in the lateral extensions where the electric field lines terminate near source and drain contacts, while the Hk material remains under the gate center. This local quality approach allows aggressive scaling without proportionally increasing stray capacitance.
3Reliability
If sacrificial-gate process is used to protect gate metal and gate insulator during annealing, then gate structure integrity is improved, but stray capacitance is greatly enhanced
Solution Approach 1:
The patent modifies the conventional sacrificial-gate process by implementing local quality differentiation in the gate dielectric. Instead of using uniform dielectric material throughout the gate region, Hk material is deposited only in the central region under the gate electrode, while Lk material is deposited in the lateral regions. This allows the sacrificial-gate process benefits to be retained while eliminating the excessive stray capacitance that would result from using Hk material throughout the entire gate region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces stray capacitances between the gate and source/drain contacts, improving the performance and reliability of field-effect transistors by optimizing the gate insulator structure and minimizing dispersion in fabrication.
Implementation Method 1
The stray capacitances tend to become particularly significant for field-effect transistors of very small dimensions... the shorter the gate length, the more the distances between the gate, on the one hand, and the contacts for the source and of the drain, on the other hand, get reduced
Data Source
AI summary
A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.