Gate Structures With Interfacial Layers For Thermal Stability
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Solution Overview
Problem
High-k gate dielectric materials face challenges in forming a uniform, defect-free interface with semiconductor channel regions, leading to increased oxygen vacancies, thermal instability, and reduced carrier mobility, which can be exacerbated by unintended oxidation and thickness issues of the interfacial layer.
Innovation Solution
An interfacial layer is formed between the channel region and the high-k gate dielectric, with precise control over its thickness to prevent unintended oxidation and diffuse oxygen out, using techniques like chemical oxidation and ALD, and subsequent annealing processes to reduce the interfacial layer thickness and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If high-k gate dielectric materials are used to replace silicon oxide, then transistor performance and thermal stability are improved, but interface uniformity and reliability deteriorate due to oxygen vacancies and defects
Solution Approach 1:
An interfacial layer is introduced between the silicon channel and the high-k gate dielectric material. This interfacial layer acts as a mediator that prevents direct contact between the silicon and high-k material, thereby reducing oxygen vacancies and interface defects while maintaining thermal stability. The interfacial layer serves as a buffer that improves interface uniformity without sacrificing the thermal benefits of high-k materials.
Solution Approach 2:
The gate dielectric structure is formed as a composite of multiple layers: a silicon oxide interfacial layer combined with a high-k dielectric layer. This composite structure combines the advantages of both materials - the silicon oxide provides a high-quality interface with low defect density, while the high-k layer provides superior thermal stability and dielectric properties.
2Reliability
If the interfacial layer thickness is increased to improve interface quality, then oxygen vacancies are reduced, but carrier mobility and device responsiveness deteriorate
Solution Approach 1:
The thickness of the interfacial layer is precisely controlled within a narrow range (approximately 1-3 nanometers). By optimizing this critical parameter, the patent achieves a balance where the interfacial layer is thick enough to reduce oxygen vacancies and improve interface quality, yet thin enough to maintain good carrier mobility and device responsiveness. This precise parameter control resolves the contradiction between interface quality and carrier transport.
3Manufacturing precision
If chemical oxidation is used to form the interfacial layer, then interface uniformity is improved, but process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent replaces mechanical or physical deposition methods with chemical oxidation to form the interfacial layer. Chemical oxidation provides superior interface uniformity and quality by chemically bonding silicon atoms in a controlled manner. Although this increases process complexity, it is offset by the significant improvements in interface quality and device performance, making the additional process steps justified.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity, reliability, and performance of transistors by reducing oxygen vacancies, improving thermal stability, and maintaining responsiveness, while balancing the benefits and costs of the interfacial layer.
Implementation Method 1
diffuse oxygen out
Implementation Method 2
subsequent annealing processes
Data Source
AI summary
Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.