Gate Isolation Structure for Metal Gate CD Control

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Solution Overview

Problem

Existing technologies face issues with critical dimension shrinkage of metal gate layers due to processing variations, leading to undesired lateral expansion of gate cut trenches, which adversely affect process windows and contact formation in semiconductor devices.

Innovation Solution

Forming dummy fins with a v-shaped top surface or two layers of different etching selectivities to limit lateral expansion of gate cut trenches, ensuring the integrity of metal gate layers by blocking undesired expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional gate isolation structures are used, then manufacturing process is simple, but critical dimension shrinkage of metal gate layers occurs due to processing variations

Engineering Contradiction:
Improvecritical dimension of metal gate layersVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate isolation structure is formed in advance before the metal gate layers are deposited. This preliminary formation of the isolation structure with precise dimensions establishes a foundation that prevents subsequent lateral expansion during processing, thereby maintaining critical dimensions of the metal gate layers without requiring complex in-process adjustments

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate isolation structure acts as an intermediary element between the substrate and the metal gate layers. By positioning this isolation structure with precise critical dimensions, it serves as a physical barrier that mediates and prevents unwanted lateral expansion of the metal gate layers during subsequent processing steps

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If conventional gate isolation structures are used, then fabrication process is straightforward, but lateral expansion of gate cut trenches occurs adversely affecting process windows

Engineering Contradiction:
Improveprocess windowVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention changes the critical dimension parameter of the gate isolation structure to be larger than conventional structures. This parameter change creates a buffer zone that compensates for processing variations and prevents lateral expansion of gate cut trenches, thereby maintaining adequate process windows without requiring complex fabrication adjustments

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If conventional gate isolation structures are used, then manufacturing is simple, but contact formation is adversely affected due to lateral expansion

Engineering Contradiction:
Improvecontact formation precisionVSAvoidgate isolation structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate isolation structure is preliminarily formed with extended dimensions before contact formation steps. This advance preparation creates defined boundaries that prevent lateral expansion during subsequent processing, ensuring precise contact formation without requiring complex real-time adjustments during contact fabrication

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250324748A1Semiconductor devices with gate isolation structures and methods of manufacturing thereof
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250324748A1 patent drawing
  • US20250324748A1 patent drawing
  • US20250324748A1 patent drawing

AI summary

A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.