Self-Aligned Gate Isolation Fins for Dense Multigate Layouts

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Solution Overview

Problem

Non-self-aligned gate cutting techniques in multigate devices hinder dense packing of IC features, leading to increased spacing between active device areas and reduced pattern density, which is not suitable for advanced IC technology nodes.

Innovation Solution

A self-aligned gate cutting technique using an oxide liner for improved inner spacer formation and a two-step process to form a dielectric gate isolation fin, allowing for smaller spacing between active device areas and enhancing suspended channel layer uniformity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If non-self-aligned gate cutting techniques are used to isolate gates of different GAA devices, then gate isolation is achieved, but spacing between active device areas increases and pattern density decreases

Engineering Contradiction:
Improvegate isolationVSAvoidspacing between active device areas
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The gate structure itself serves as the alignment reference for the isolation fin formation. The isolation fin is self-aligned to the gate, eliminating the need for separate alignment processes and reducing spacing requirements between active device areas.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The method performs gate isolation formation in advance during the GAA device fabrication process, integrating it with the gate structure formation rather than treating it as a subsequent separate step. This preliminary integration enables tighter packing.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If non-self-aligned gate cutting techniques are used, then gate isolation is achieved, but pattern density is reduced

Engineering Contradiction:
Improvegate isolationVSAvoidpattern density
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The gate structure provides the alignment reference for isolation fin formation, making the process self-aligned and eliminating wasted space, thereby increasing pattern density for advanced IC technology nodes.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The gate isolation formation is merged with the gate structure fabrication process. The isolation fin is formed as an integrated part of the gate structure rather than as a separate post-processing step, improving pattern density.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If oxide liner is used for inner spacer formation, then suspended channel layer uniformity is improved, but process complexity increases

Engineering Contradiction:
Improvesuspended channel layer uniformityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The oxide liner acts as an intermediary layer between the sacrificial layer and the inner spacer. It provides a controlled interface that ensures uniform inner spacer formation and suspended channel layer uniformity while managing the complexity through a defined deposition and removal sequence.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250254987A1Gate isolation for multigate device
Publication Date: 2025.08.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250254987A1 patent drawing
  • US20250254987A1 patent drawing
  • US20250254987A1 patent drawing

AI summary

Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.