Self-Aligned Gate Isolation Structure for Nanosheet FET Endcap Reduction
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Solution Overview
Problem
The challenge in advanced technology nodes is forming contacts and vias to the gate, source, and drain electrodes of field-effect transistors (FETs) due to increased active area spacing and overlap shift during gate isolation structure formation, leading to difficulties in reducing the endcap and maintaining device performance.
Innovation Solution
A self-aligned gate isolation structure is formed by recessing a first gate metal, selectively growing a second gate metal, and depositing the isolation structure between neighboring gate structures, with an anneal process to increase the lateral thickness of the interfacial layer, allowing for reduced thickness of the second gate metal and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate isolation structure is formed with conventional methods, then electrical isolation between neighboring gate structures is achieved, but active area spacing increases and overlap shift occurs during formation
Solution Approach 1:
The gate isolation structure is formed before the gate electrodes are fully patterned. The isolation structure is deposited in openings between neighboring gate structures, and then the gate electrodes are patterned to their final positions. This preliminary formation of the isolation structure prevents overlap shift during subsequent processing steps.
Solution Approach 2:
A sacrificial material is used as an intermediary to define the position of the gate isolation structure. The sacrificial material is deposited in the openings between neighboring gate structures, and then removed to create voids that are filled with the gate isolation structure material. This intermediary approach ensures precise positioning and electrical isolation.
2Area of moving object
If endcap is reduced to minimize device area, then nanostructure device area is decreased, but manufacturing difficulty increases due to alignment requirements
Solution Approach 1:
The gate isolation structure formation process is self-aligned to the gate electrode pattern. The openings for the isolation structure are defined by the gate electrode pattern itself, eliminating the need for separate alignment steps. This self-aligned approach reduces the endcap while maintaining manufacturing ease.
Solution Approach 2:
The gate electrode pattern is established before the gate isolation structure is formed. This preliminary patterning of the gate electrodes defines the precise positions where the isolation structure will be deposited, ensuring accurate alignment and minimizing the endcap without requiring complex alignment procedures.
3Manufacturing precision
If gate isolation structure is offset from semiconductor channels, then overlap shift is prevented, but device performance is compromised due to increased spacing
Solution Approach 1:
The gate isolation structure is positioned to provide localized electrical isolation between neighboring gate structures while maintaining optimal spacing from the semiconductor channels. The isolation structure is formed in openings between gate structures, providing targeted isolation without unnecessarily increasing overall device spacing or compromising channel performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the endcap, minimizing the nanostructure device area and enhancing performance by aligning the gate isolation structure, thus improving electrical isolation and reducing overlap shift.
Implementation Method 1
an anneal process to increase the lateral thickness of the interfacial layer
Data Source
AI summary
A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.