Gate Isolation Fin Structure for Dense Multigate Layouts
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Solution Overview
Problem
Non-self-aligned gate cutting techniques in multigate devices hinder the dense packing of IC features needed for advanced IC technology nodes, leading to increased spacing between active device areas and reduced pattern density.
Innovation Solution
A self-aligned gate cutting technique is employed, using a gate isolation fin with a low-k dielectric core surrounded by a high-k dielectric shell, which allows for smaller spacing between active device areas and improves gate isolation, reducing void formation and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-self-aligned gate cutting techniques are used to isolate gates of different multigate devices, then gate isolation is achieved, but spacing between active device areas increases and pattern density decreases
Solution Approach 1:
The gate isolation fin structure performs self-alignment during fabrication, where the isolation fin automatically positions itself relative to the gate without requiring additional alignment steps. This self-service mechanism eliminates the need for non-self-aligned cutting techniques while maintaining proper gate isolation, thereby reducing spacing requirements between active device areas
Solution Approach 2:
The gate isolation fin is nested within the trench structure formed between adjacent multigate devices. The isolation fin fits into the available space without requiring additional lateral spacing, effectively utilizing the vertical dimension for isolation while maintaining compact horizontal dimensions for dense packing
2Ease of manufacture
If conventional gate isolation techniques are used, then manufacturing process simplicity is maintained, but dense packing of IC features is hindered
Solution Approach 1:
The gate isolation fin formation is merged with the existing trench isolation process flow. The same trench etching and filling steps that create device isolation are used to form the gate isolation fin, combining multiple functions into a single integrated process sequence that maintains manufacturing simplicity while enabling dense packing
Solution Approach 2:
The gate isolation fin structure serves multiple functions: it provides gate-to-gate isolation, acts as a spacer during subsequent processing steps, and defines alignment references for overlying layers. This multi-functionality eliminates the need for separate isolation processes, maintaining ease of manufacture while improving pattern density
Data Source
AI summary
Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.