Gate Isolation Fins for Dense Multigate Metal Gate Layouts
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Solution Overview
Problem
Existing multigate device manufacturing techniques face challenges in achieving dense packing of IC features due to non-self-aligned gate cutting methods, which result in increased spacing between active device areas, leading to reduced pattern density and performance limitations.
Innovation Solution
A self-aligned gate cutting technique is introduced, utilizing gate isolation fins with a low-k dielectric core surrounded by a high-k dielectric shell to improve gate isolation and reduce spacing between active device areas, enhancing the performance of multigate devices by minimizing void formation and improving gate-drain capacitance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-self-aligned gate cutting techniques are used to isolate gates of different devices, then gate isolation is achieved, but spacing between active device areas increases, reducing pattern density
Solution Approach 1:
The gate isolation fin is formed in advance before the gates of adjacent devices are completely defined. By pre-positioning the isolation fin between potential gate locations, the subsequent gate formation process can proceed with self-alignment, eliminating the need for additional spacing that would be required in non-self-aligned processes.
Solution Approach 2:
The gate isolation fin structure serves dual purposes: it provides electrical isolation between adjacent gates while simultaneously defining the precise location and alignment of the gates themselves. The isolation fin acts as a self-aligning reference feature that guides the formation of adjacent gates, eliminating the need for separate alignment processes and reducing spacing requirements.
2Reliability
If larger spacing is provided between active device areas to accommodate non-self-aligned gate cutting, then gate isolation is maintained, but pattern density and device performance decrease
Solution Approach 1:
The gate isolation fin is formed in advance before the gates of adjacent devices are completely defined. By pre-positioning the isolation fin between potential gate locations, the subsequent gate formation process can proceed with self-alignment, eliminating the need for additional spacing that would be required in non-self-aligned processes.
Solution Approach 2:
The gate isolation fin structure serves dual purposes: it provides electrical isolation between adjacent gates while simultaneously defining the precise location and alignment of the gates themselves. The isolation fin acts as a self-aligning reference feature that guides the formation of adjacent gates, eliminating the need for separate alignment processes and reducing spacing requirements.
3Ease of manufacture
If non-self-aligned gate cutting is used, then manufacturing process is simpler, but void formation increases and gate-drain capacitance performance deteriorates
Solution Approach 1:
The gate isolation fin is formed in advance before the gates of adjacent devices are completely defined. By pre-positioning the isolation fin between potential gate locations, the subsequent gate formation process can proceed with self-alignment, eliminating the need for additional spacing that would be required in non-self-aligned processes.
Solution Approach 2:
The gate isolation fin structure serves dual purposes: it provides electrical isolation between adjacent gates while simultaneously defining the precise location and alignment of the gates themselves. The isolation fin acts as a self-aligning reference feature that guides the formation of adjacent gates, eliminating the need for separate alignment processes and reducing spacing requirements.
Data Source
AI summary
Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.