Gate Isolation Layer Layout to Prevent FinFET Gate Line Loss
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Solution Overview
Problem
As semiconductor devices become more densely integrated, it is challenging to achieve the required transistor performance, necessitating innovative FET structures such as high-k dielectric-metal gate structures to replace conventional silicon oxide and polycrystalline silicon gate insulating layers and electrodes.
Innovation Solution
The semiconductor device incorporates a substrate with distinct regions, active fins, field insulating layers, a gate line, a gate isolation layer, and gate spacers, with optimized diffusion break regions in both PMOS and NMOS regions to enhance performance and prevent gate line loss during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon oxide and polycrystalline silicon gate insulating layers and electrodes are used, then manufacturing process is simple, but transistor performance is insufficient for high integration density
Solution Approach 1:
The patent employs a composite gate structure consisting of a high-k dielectric layer (such as hafnium oxide, zirconium oxide, or tantalum oxide) combined with a metal gate electrode (such as tungsten, molybdenum, or titanium nitride). This composite material approach enables superior transistor performance and higher integration density while maintaining manufacturability through established semiconductor fabrication processes.
2Productivity
If integration density is increased, then device capacity improves, but gate line loss during manufacturing occurs
Solution Approach 1:
The patent introduces a gate isolation layer formed between the field insulating layer and the gate line before completing the gate structure fabrication. This preliminary protective action prevents gate line loss that would otherwise occur during subsequent manufacturing steps, thereby maintaining gate line stability while enabling higher integration density.
Solution Approach 2:
The gate isolation layer serves as an intermediary protective element between the field insulating layer and the gate line. This intermediate structure prevents direct exposure of the gate line to manufacturing processes that could cause line loss, thus preserving gate line integrity in high-density device configurations.
3Manufacturing precision
If field insulating layer is placed between active fins, then diffusion control is improved, but gate line fabrication becomes difficult
Solution Approach 1:
The patent segments the insulating structure by placing the gate isolation layer between the field insulating layer and the gate line. This segmentation creates distinct functional zones that maintain precise diffusion control through the field insulating layer while simplifying gate line fabrication by providing a dedicated isolation interface.
Data Source
AI summary
A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.