Gate Isolation Circuit for GHz DUT Reliability Testing
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Solution Overview
Problem
Existing reliability tests for semiconductor devices are limited to clock signals in the MHz range due to significant parasitic capacitance, making it challenging to perform tests on devices operating in the GHz range.
Innovation Solution
A test circuit is developed that includes a clock generator capable of generating clock signals in the GHz range, a gate control circuit to convert voltage levels, and a gate isolation circuit to prevent interference from parasitic capacitance, allowing for reliable stress testing of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signals in the GHz range are applied to the DUT for reliability testing, then test frequency and reliability assessment accuracy are improved, but parasitic capacitance effects increase causing signal degradation and measurement errors
Solution Approach 1:
An isolation circuit is introduced as an intermediary component between the clock signal source and the DUT gate terminal. This isolation circuit acts as a mediator that blocks parasitic capacitance effects from propagating to the measurement system while allowing the high-frequency clock signal to pass through to the DUT for reliable GHz-range testing.
Solution Approach 2:
The test system is divided into separate functional segments: a clock signal generation section, an isolation section with the isolation circuit, and a measurement section. This segmentation allows each component to be optimized independently - the isolation circuit specifically addresses parasitic capacitance issues while the measurement section focuses on accurate leakage current detection at high frequencies.
2Measurement precision
If direct measurement of gate leakage current is performed without isolation, then measurement simplicity is maintained, but measurement precision deteriorates due to parasitic capacitance interference
Solution Approach 1:
The isolation circuit serves as a mediator that improves measurement precision by eliminating parasitic capacitance interference from the measurement path. Although this adds circuit complexity, the isolation circuit is designed to be integrated and compact, minimizing the increase in overall device complexity while significantly enhancing gate leakage current measurement accuracy at GHz frequencies.
Data Source
AI summary
The present disclosure provides an integrated circuit, which includes a device under test (DUT) and a test circuit. The test circuit includes a clock generator, a gate control circuit, and a gate isolation circuit. The clock generator is configured to generate a clock signal. The gate control circuit is configured to convert, in response to a test enable signal being deasserted, the clock signal within a first voltage domain to generate a gate clock signal within a second voltage domain at an output terminal of the gate control circuit which is connected to a gate terminal of the DUT. The gate isolation circuit is coupled between the gate terminal of the DUT and a first input/output (I/O) pad of the integrated circuit.