Gate Isolation Structure for Multi-Gate Transistors
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Solution Overview
Problem
As semiconductor devices shrink, parasitic capacitance between adjacent gate structures in multi-gate transistors increases, slowing down switching speed and reducing the gate fill window, which complicates the formation of satisfactory gate structures.
Innovation Solution
A method is introduced to form a gate isolation structure by depositing gate structure layers over a dielectric fin, planarizing, and then removing the dielectric fin to create an isolation trench, allowing direct contact between the gate isolation structure and gate electrode layers, thereby reducing parasitic capacitance without sacrificing the gate formation window or yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the width of gate cut feature or dielectric fin is increased to reduce parasitic capacitance between adjacent gate structures, then parasitic capacitance is reduced, but the gate fill window is reduced making it difficult to form satisfactory gate structures
Solution Approach 1:
The gate isolation structure is divided into two distinct portions: a lower portion that provides parasitic capacitance reduction and an upper portion that maintains gate fill window. This segmentation allows each portion to independently fulfill its specific function without compromising the other, resolving the contradiction between reducing parasitic capacitance and maintaining ease of gate structure formation
Solution Approach 2:
The gate isolation structure transitions from a conventional single-level dielectric fin to a two-level structure with lower and upper portions at different vertical dimensions. The lower portion extends between gate structures to reduce capacitance, while the upper portion rises to preserve the gate fill window, effectively using vertical dimensionality to resolve the horizontal trade-off
2Ease of manufacture
If conventional gate cut features or dielectric fins are used, then gate formation is satisfactory, but parasitic capacitance between adjacent gate structures increases
Solution Approach 1:
The gate isolation structure is divided into two distinct portions: a lower portion that provides parasitic capacitance reduction and an upper portion that maintains gate fill window. This segmentation allows each portion to independently fulfill its specific function without compromising the other, resolving the contradiction between reducing parasitic capacitance and maintaining ease of gate structure formation
Solution Approach 2:
The gate isolation structure transitions from a conventional single-level dielectric fin to a two-level structure with lower and upper portions at different vertical dimensions. The lower portion extends between gate structures to reduce capacitance, while the upper portion rises to preserve the gate fill window, effectively using vertical dimensionality to resolve the horizontal trade-off
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.