Gate Isolation Openings With Conformal Layer CD Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing device size and improving performance while minimizing defects, particularly in forming isolation structures and gate electrodes, due to limitations in current methods for etching and patterning in the manufacturing of FinFETs and nanostructure field-effect transistors.
Innovation Solution
The method involves forming a conformal layer over a gate structure, using atomic layer deposition techniques, to narrow openings and improve etch selectivity, allowing for precise control of critical dimensions and reduced scum formation, thereby enhancing device performance and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional etching and patterning methods are used, then device fabrication can proceed with standard processes, but device size cannot be sufficiently reduced and critical dimension control is poor
Solution Approach 1:
A conformal layer is deposited over the gate structure before the etching process to pre-narrow the openings. This preliminary action of depositing the conformal layer allows the subsequent etch process to achieve better critical dimension control and smaller device sizes, as the conformal layer is specifically designed to be removed selectively after serving its dimension-control function
Solution Approach 2:
The conformal layer is applied selectively over the gate structure in specific regions where opening narrowing is needed. This localized application allows different parts of the device to have different properties - the conformal layer narrows openings in critical areas while leaving other regions unchanged, thereby improving critical dimension control where it matters most
2Reliability
If conventional patterning methods are used, then standard manufacturing processes can be maintained, but scum formation occurs during etching which increases defects
Solution Approach 1:
The conformal layer acts as an intermediary between the etch process and the gate structure. It modifies the etching behavior by providing a controlled interface that prevents scum formation on the gate structure, thereby reducing defects and improving reliability without interfering with the overall etching process
Solution Approach 2:
The conformal layer is deposited in advance to prevent scum formation before it can occur during etching. This preliminary protective action counteracts the harmful effect of scum formation, allowing the etch process to proceed cleanly and reducing defect generation
3Manufacturing precision
If opening narrowing is achieved without conformal layer, then process steps are simpler, but etch selectivity and critical dimension control are insufficient
Solution Approach 1:
The conformal layer changes the physical and chemical parameters of the opening structure, including width, surface area, and etch resistance. These parameter changes enable improved etch selectivity and critical dimension control, as the conformal layer provides a controlled interface that enhances the precision of the etching process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller device sizes, improved performance, and reduced defects by providing better control over critical dimensions and minimizing scum during the etching process, leading to more efficient semiconductor device manufacturing.
Implementation Method 1
forming a conformal layer over a gate structure, using atomic layer deposition techniques
Data Source
AI summary
Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.