Gate Isolation Regions With Bottom-Up Oxide Filling for FinFETs
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Solution Overview
Problem
The formation of FinFETs involves challenges in creating seam-free gate isolation regions due to uneven deposition of silicon oxide during the etching and deposition processes, which can lead to defects and shorting of neighboring source/drain contacts.
Innovation Solution
A method using Plasma Enhanced Atomic Layer Deposition (PEALD) with controlled ammonia plasma treatment, silicon precursor soaking, and oxidation processes to achieve a bottom-up deposition of silicon oxide in trenches, ensuring uniformity and seam-free gate isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form silicon oxide in trenches, then the deposition process is simple, but the silicon oxide deposits unevenly creating seams and defects
Solution Approach 1:
The patent applies preliminary action by performing ammonia plasma treatment on the trench surfaces before silicon oxide deposition. This pre-treatment modifies the trench surface properties to promote uniform silicon oxide deposition, preventing seam formation. The plasma treatment activates the surface and creates conditions that ensure even deposition throughout the trench structure.
Solution Approach 2:
The patent employs parameter changes by controlling deposition conditions in PEALD to achieve bottom-up deposition style. By adjusting plasma power, precursor flow rates, and temperature parameters, the process ensures silicon oxide deposits from the trench bottom upward, eliminating seams that would form with conventional top-down deposition methods.
2Productivity
If fast deposition is used to increase productivity, then deposition rate increases, but seam formation and defects increase
Solution Approach 1:
The ammonia plasma treatment performed before deposition prepares the trench surfaces in advance, creating conditions that allow fast deposition without seam formation. The pre-treated surfaces ensure that even at high deposition rates, silicon oxide deposits uniformly from the bottom up, maintaining quality while increasing productivity.
Solution Approach 2:
The patent replaces conventional chemical vapor deposition with Plasma Enhanced Atomic Layer Deposition. This substitution introduces plasma activation that enables controlled bottom-up deposition, allowing faster deposition rates while maintaining high quality and preventing seam formation through the plasma-enhanced reaction mechanism.
3Reliability
If seams are present in gate isolation regions, then manufacturing is simpler, but metal intrusion occurs causing shorting of source/drain contacts
Solution Approach 1:
The patent performs preliminary ammonia plasma treatment and controlled PEALD deposition to create seam-free gate isolation regions before subsequent processing steps. This advance preparation ensures that the dielectric regions are free from seams that could allow metal intrusion, preventing contact shorting while maintaining a manageable process flow.
Solution Approach 2:
The patent uses silicon oxide deposited via controlled PEALD as an intermediary barrier in the gate isolation regions. This carefully formed dielectric layer acts as a protective intermediary that prevents direct contact between metal interconnects and source/drain regions, eliminating the shorting problem associated with seams.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in high-quality, seam-free dielectric regions with improved deposition rates, reducing defects and enhancing the reliability of FinFETs by preventing metal intrusion into seams.
Implementation Method 1
an ammonia plasma treatment process
Implementation Method 2
The ammonia plasma treatment process is controlled so that silicon oxide is deposited faster at lower parts of the trenches than at upper parts of the trenches
Implementation Method 3
a silicon precursor soaking process
Implementation Method 4
an oxidation process are performed
Data Source
AI summary
A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.