Gate Isolation Structure Layout for Leakage and Pattern Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down, existing design schemes like PODE and CPODE face challenges in achieving the required device density and performance due to issues such as current leakage and photoresist defects, particularly as gate pitch decreases.
Innovation Solution
The formation of isolation structures with non-uniform widths, including wide and narrow segments, in the gate structures to prevent photoresist peeling and pattern merge, while ensuring sufficient etch depth for effective isolation between source/drain regions and transistors, using a CPODE or CMODE process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous poly on diffusion edge (CPODE) or diffusion edge (PODE) patterns are used to avoid leakage between neighboring devices, then device leakage is reduced, but photoresist peeling and pattern merge occur as gate pitch decreases
Solution Approach 1:
The gate structure is segmented into multiple sections with different poly thicknesses. Specifically, the gate includes a first section with a first thickness and a second section with a second thickness different from the first. This segmentation allows different regions to serve different functions: thicker regions provide better leakage prevention while thinner regions prevent photoresist peeling and pattern merge during fabrication.
Solution Approach 2:
Different portions of the gate structure are given different local properties through varying poly thickness. The gate structure has non-uniform poly thickness distribution, with thicker regions at specific locations (such as at the diffusion edge) to enhance leakage prevention, and thinner regions in other areas to maintain photoresist pattern integrity during scaling.
2Productivity
If gate pitch is reduced to increase device density, then device density increases, but design schemes like PODE and CPODE face difficulties in providing required device density and performance
Solution Approach 1:
The gate is divided into multiple sections with varying poly thicknesses, allowing the structure to maintain effective isolation at reduced gate pitches. The segmented design enables the thinner sections to fit within scaled dimensions while thicker sections maintain isolation performance, thus achieving both high device density and reliable device performance.
Solution Approach 2:
The poly thickness parameter is varied across different sections of the gate structure. By changing the thickness parameter locally rather than uniformly, the design achieves better isolation effectiveness at scaled dimensions, enabling continued scaling while maintaining device performance requirements.
3Reliability
If isolation structures are formed with sufficient etch depth to prevent current leakage, then isolation effectiveness increases, but fabrication complexity increases
Solution Approach 1:
The mask pattern is designed in advance with varying opening widths corresponding to the different poly thickness sections. The wider opening aligns with the thicker poly section to enable sufficient etch depth for isolation, while the narrower opening aligns with the thinner poly section. This preliminary design of the mask pattern simplifies the fabrication process by pre-planning the etch depth requirements for different regions.
Solution Approach 2:
The etch process is applied locally with different depths in different regions of the gate structure. The isolation structure extends to different depths beneath the first and second sections of the gate, with greater depth under thicker poly sections. This localized etching approach achieves effective isolation where needed while avoiding unnecessary complexity in regions where isolation is less critical.
Data Source
AI summary
Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.