Gate Isolation Structure Layout for Leakage Control at Reduced Pitch
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology process nodes, challenges arise in achieving the required device density, cell isolation, and performance due to the scaling down of gate pitch in multi-gate devices like FinFETs and GAA transistors.
Innovation Solution
The solution involves forming isolation structures in gate structures using a CPODE or CMODE process, which includes creating a pattern with varying lengths of isolation openings and applying tensile stress to the substrate, along with a passivation-oriented etch process to prevent photoresist peeling and ensure effective isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate pitch is reduced to increase device density, then device density improves, but manufacturing precision and photoresist stability deteriorate
Solution Approach 1:
The gate structure is segmented into multiple sections with different isolation opening lengths (first section with first length, second section with second length). This segmentation allows different regions to have optimized isolation characteristics, enabling reduced gate pitch while maintaining photoresist stability through the specifically designed shorter isolation openings in critical regions.
Solution Approach 2:
Different sections of the gate structure have different isolation opening lengths tailored to local requirements. The first section has isolation openings of a first length while the second section has isolation openings of a second length (shorter than the first). This local differentiation provides enhanced photoresist stability in areas where it is most needed, allowing overall gate pitch reduction without compromising manufacturing precision.
2Reliability
If isolation structures are formed to prevent leakage between devices, then device isolation improves, but device complexity and fabrication difficulty increase
Solution Approach 1:
The isolation structures are segmented into different length portions (first length and second length) corresponding to different gate sections. This segmentation provides effective leakage prevention through the isolation dielectric material while keeping the structure relatively simple by using only two distinct length values rather than continuous variation.
Solution Approach 2:
Instead of making all isolation openings uniformly long to ensure isolation, the invention uses shorter isolation openings in the second section where leakage risk is lower, and longer openings in the first section where isolation is critical. This inverted approach to uniformity reduces overall structure complexity while maintaining necessary isolation performance.
3Reliability
If continuous poly on diffusion edge (CPODE) is used to avoid leakage, then device reliability improves, but manufacturing precision and pattern control deteriorate at scaled dimensions
Solution Approach 1:
The CPODE structure is segmented into sections with different isolation opening lengths. This segmentation maintains the continuous poly leakage prevention benefit while improving pattern control by introducing variation in isolation opening lengths that compensates for scaling effects and provides better manufacturability at reduced dimensions.
Data Source
AI summary
Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures are arranged in a pattern with a long isolation structure adjacent a short isolation structure. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.