Gate Isolation Stack Layout for Denser Integrated Circuits
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Solution Overview
Problem
The challenge in integrated circuit devices is to reduce the size of the isolation region between adjacent transistors to enhance integration density while maintaining desired performance, and existing methods require cumbersome processes for forming isolation regions.
Innovation Solution
The integration circuit device employs a fin-type active region with conductive stack structures and isolation stack structures using metal nitride layers with different effective work functions, allowing for reduced isolation area and simplified fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the isolation region is reduced to increase integration density, then integration density is improved, but electrical insulation between adjacent transistors may be compromised
Solution Approach 1:
The patent applies local quality by forming an isolation stack structure with a different work function metal layer than the gate stack structures. Specifically, the isolation stack structure includes a first work function metal layer with a first work function, while the gate stack structures include a second work function metal layer with a second work function that is different from the first work function. This local differentiation in material properties enables the isolation structure to provide effective electrical insulation between adjacent transistors while maintaining compact dimensions, thus resolving the contradiction between integration density and electrical insulation reliability.
2Reliability
If conventional isolation region formation processes are used, then electrical insulation is achieved, but the fabrication process becomes cumbersome and complex
Solution Approach 1:
The patent merges the isolation structure formation with the gate structure formation processes. Both the gate stack structures and the isolation stack structure are formed simultaneously using the same sequence of steps: forming the same insulating structure defining gate spaces, depositing the same tunnel barrier layer, depositing the work function metal layers (with selective masking to place different materials in different locations), depositing the same gate electrode layer, and forming the same capping layer. This consolidation eliminates separate, cumbersome isolation formation processes while ensuring reliable electrical insulation through the work function difference between the isolation and gate metal layers.
3Area of stationary object
If the isolation region area is reduced, then device area is minimized for higher integration, but the fabrication process requires additional precise control steps
Solution Approach 1:
The patent employs universal process steps that serve multiple functions simultaneously. The same insulating structure serves as both the gate spacer and the isolation structure base. The same tunnel barrier layer deposition process forms barriers for both gate and isolation stacks. The work function metal layer deposition uses selective masking to simultaneously define both gate electrodes and isolation structures in a single process sequence. This multi-functionality approach enables precise control of the isolation region area without requiring additional specialized process steps, as the isolation structure is created as an integrated part of the gate formation process rather than as a separate feature requiring independent control.
Data Source
AI summary
An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.