Self-Aligned Gate Isolation Using Width-Selective Trench Filling

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Solution Overview

Problem

Conventional fabrication processes for self-aligned gate structures in quantum and semiconductor devices fail to implement intersection elements or terminals while maintaining high gate density, especially when dealing with multiple 1D chains or locally linear qubit arrays.

Innovation Solution

A method for fabricating a self-aligned gate structure with multiple metallic gate electrodes involves forming trenches with different widths, depositing a conformal dielectric layer that completely fills narrower trenches and partially fills wider ones, and then depositing a second metallic gate layer that fills the unfilled portions of the wider trenches, followed by etching to expose the dielectric layer and create self-aligned gate electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication processes are used for self-aligned gate structures, then manufacturing simplicity is maintained, but gate density and multi-directional connectivity cannot be achieved

Engineering Contradiction:
Improvegate densityVSAvoidfabrication complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate structure is divided into two separate metallic gate layers (first and second metallic gate layers) with different orientations. The first metallic gate layer contains gate electrodes in a first direction, while the second metallic gate layer contains gate electrodes in a second direction. This segmentation enables multi-directional connectivity and high gate density while maintaining self-alignment through the conformal dielectric layer that fills trenches between gates in each layer independently.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If intersection elements are implemented in gate structures, then multi-directional connectivity is achieved, but fabrication complexity increases

Engineering Contradiction:
Improvemulti-directional connectivityVSAvoidfabrication complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent transitions from a single-plane gate structure to a three-dimensional stacked architecture with two metallic gate layers at different vertical levels. The first metallic gate layer is positioned at a first vertical level with gates in a first direction, while the second metallic gate layer is positioned at a second vertical level with gates in a second direction. This dimensional transition enables intersection elements and T-junctions without increasing fabrication complexity, as the conformal dielectric layer automatically provides isolation and alignment for both layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If gate density is increased, then device functionality is improved, but processing damage occurs

Engineering Contradiction:
Improvegate densityVSAvoidprocessing damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The conformal dielectric layer performs multiple functions automatically: it fills trenches between gate electrodes in the first metallic gate layer, provides electrical isolation, and serves as a template for the second metallic gate layer. This self-aligning mechanism eliminates the need for additional alignment steps and reduces processing complexity, enabling high gate density without increasing processing damage.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the implementation of intersection elements and terminals in a scalable self-aligned gate structure with high gate density, reducing fabrication complexity and processing damage, while maintaining alignment tolerance and uniformity.

Implementation Method 1

depositing at least one conformal dielectric layer on the first metallic gate layer, where the at least one conformal dielectric layer completely fills the at least one first trench, and the at least one conformal dielectric layer partially fills the at least one second trench

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS20250040232A1Self-aligned gate isolation for multi-directional gate layouts in quantum and semiconductor devices
Publication Date: 2025.01.30 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20250040232A1 patent drawing
  • US20250040232A1 patent drawing
  • US20250040232A1 patent drawing

AI summary

One embodiment of the invention provides a method for fabricating a self-aligned gate structure comprising forming at least one first trench having a first width and at least one second trench having a second width in a gate structure comprising a first metallic gate layer. The first width is smaller than the second width. The method comprises depositing at least one conformal dielectric layer on the first metallic gate layer. The dielectric layer completely fills the first trench and partially fills the second trench, such that a portion of the second trench is unfilled. The method comprises depositing a conformal second metallic gate layer on the dielectric layer. The second metallic gate layer fills the unfilled portion of the second trench. The method comprises removing portions of the second metallic gate layer to expose the dielectric layer. Remaining portions of the second metallic gate layer include self-aligned metallic gate electrodes.