Gate-Last Process Gate Height Control via Capping Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In gate-last semiconductor processes, controlling the height distribution of gates is challenging due to reduced IC size, leading to issues like resistance defects, source/drain exposure, contamination, and dummy gate removal defects, particularly because of variations in gate mask removal processes.
Innovation Solution
A method involving chemical mechanical polishing (CMP) of interlayer dielectrics, selective etching of gate masks, and deposition of a capping interlayer dielectric to achieve a uniform top surface, minimizing gate height loss and distribution variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate mask removal is performed by etching, then gate mask can be removed, but local dents are generated in the upper portion of the spacer due to over-etching
Solution Approach 1:
A capping layer is deposited over the spacer before gate mask removal. This preliminary action protects the spacer from over-etching damage while allowing complete gate mask removal. The capping layer is subsequently removed to reveal the intact spacer structure.
Solution Approach 2:
The capping layer serves as an intermediary protective layer between the etching process and the spacer. It absorbs the etching action that would otherwise damage the spacer, enabling precise gate mask removal without compromising spacer integrity.
2Productivity
If gate height is reduced due to gate-last process, then IC size reduction is achieved, but gate height distribution becomes wide leading to defects
Solution Approach 1:
The capping layer is deposited before gate formation to establish a uniform reference plane. This preliminary action ensures that subsequent gate formation processes start from a consistent height baseline, resulting in narrow gate height distribution even as overall IC size is reduced.
Solution Approach 2:
The process changes the height parameter of the underlying structure by adding the capping layer, which compensates for height variations. This parameter change enables precise control of gate height distribution while maintaining reduced IC dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the distribution in gate height, minimizing defects and ensuring consistent gate formation by compensating for local dents and dishing, thereby improving process efficiency and reducing subsequent process burdens.
Implementation Method 1
performing a first chemical mechanical polishing (CMP) on a first interlayer dielectric (ILD)
Implementation Method 2
removing the gate mask by etching the gate mask
Data Source
AI summary
Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.