Gate-Last Semiconductor Device With Dielectric Cap Layer
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in filling high-K gate dielectrics and metal gate materials into nano-scale gate grooves with aspect ratios greater than 1, leading to non-uniformity and high gate resistance, particularly at the 22 nm node and below, due to step coverage issues during thin film deposition.
Innovation Solution
A method is introduced where a semiconductor device is manufactured by forming a dummy gate, spacers, and source/drain areas, followed by planarization with a dielectric cap layer to control the gate groove thickness, allowing for the formation of replacement gates with reduced aspect ratio and low gate resistance, maintaining the advantages of the gate-last process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate groove aspect ratio is reduced to improve filling capability, then the uniformity of metal gate layer and high-K gate dielectric layer improves, but the gate resistance increases
Solution Approach 1:
The patent introduces a lateral dimension solution by forming the gate electrode to extend beyond the gate groove boundaries in the lateral direction. This dimensional extension allows the gate electrode to be formed with lower aspect ratio requirements while maintaining adequate gate coverage and electrical performance, thus resolving the contradiction between filling uniformity and gate resistance
Solution Approach 2:
The gate structure is segmented into multiple components: the gate electrode formed in the gate groove, and the additional gate electrode portions extending laterally beyond the groove. This segmentation allows optimization of each part independently - the groove portion ensures proper dielectric filling while the extended portions provide low-resistance electrical pathways
2Manufacturing precision
If deposition conditions are optimized to overcome step coverage, then the filling capability improves, but the process complexity increases
Solution Approach 1:
The patent performs preliminary structural preparation by forming the gate groove with controlled dimensions and characteristics before the deposition process. By pre-optimizing the groove geometry (width, depth, sidewall angle), the subsequent deposition process becomes simpler and more reliable, reducing the need for complex deposition condition optimization
Data Source
AI summary
A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.