Gate-Last Semiconductor Device Planarization via Reactive Ion Etching
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Solution Overview
Problem
The gate-last process for semiconductor device manufacturing involves a complex and costly Chemical Mechanical Polishing (CMP) process to achieve a planar Interlayer Dielectric (ILD) layer, which reduces the available wafer area due to non-uniform etching of the spin-on glass (SOG) layer, leading to convex etching profiles and edge discard.
Innovation Solution
A method using reactive ion etching (RIE) with controlled reaction chamber pressure and RF power to achieve a concave etching profile, followed by additional RIE steps to compensate for overetching, replacing the CMP process and ensuring a planar ILD layer without the need for expensive CMP equipment, thereby increasing the available wafer area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to achieve planar ILD layer, then surface flatness is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent replaces the mechanical CMP (Chemical Mechanical Polishing) process with a chemical etching process using RIE (Reactive Ion Etching) to achieve planarization. This substitution eliminates the need for mechanical polishing equipment and reduces process complexity while maintaining surface flatness requirements.
Solution Approach 2:
The patent changes the etching parameters (reaction chamber pressure, RF power) to control the etching rate and achieve a concave etching profile that compensates for the natural convex profile, thereby obtaining a planar surface without CMP process.
2Manufacturing precision
If CMP process is used to achieve planar ILD layer, then surface flatness is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces the expensive CMP process with a chemical etching process using RIE, which uses standard semiconductor manufacturing equipment and chemicals, thereby reducing manufacturing cost while achieving the required surface flatness for subsequent metal gate deposition.
Solution Approach 2:
The patent uses a sacrificial SOG layer that is etched away to create the planar surface. This disposable layer enables planarization through etching rather than requiring expensive CMP equipment, reducing overall manufacturing cost.
3Manufacturing precision
If SOG layer is etched to planarize surface, then surface flatness is improved, but convex etching profile reduces available wafer area
Solution Approach 1:
The patent inverts the expected etching profile from convex to concave by controlling RIE parameters (higher pressure, lower RF power). This concave profile compensates for the natural convex profile formed during etching, resulting in a planar surface that maximizes the available wafer area and prevents edge discard.
Solution Approach 2:
The patent changes the etching parameters (reaction chamber pressure increased to 30-100 mTorr, RF power decreased to 50-200W) to achieve a concave etching profile instead of the conventional convex profile, thereby maintaining surface flatness while preserving maximum wafer area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces costs, and achieves global planarization by eliminating the conformal characteristic of the ILD layer, ensuring a larger available wafer area and improved manufacturing efficiency.
Implementation Method 1
performing a first reactive ion etching (RIE) on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer
Data Source
AI summary
A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.