Gate-Last Process for Reducing Parasitic Capacitance in Semiconductor Devices
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Solution Overview
Problem
The miniaturization of MOS transistors in semiconductor integrated circuits leads to increased difficulty in suppressing leak current and reducing the area occupied by the circuit while maintaining the required current, necessitating a more efficient method for producing surrounding gate transistors (SGTs) that integrates a metal gate process with a high-temperature process and reduces parasitic capacitance.
Innovation Solution
A gate-last process using two masks to form a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, and a gate electrode, which involves forming insulating films, polysilicon layers, and dummy gates to create a metal-semiconductor compound and gate electrode, allowing for the reduction of parasitic capacitance and misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three masks are used to form silicon pillar, planar silicon layer, and gate line separately, then each component can be formed with precise control, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent combines the formation of the gate line and pillar-shaped semiconductor layer into a single etching step using one mask pattern. The mask is designed with regions that define both the gate line position and the pillar-shaped layer position, allowing simultaneous formation of both structures from a single deposited layer, thereby reducing the number of masks from three to one while maintaining precision control.
Solution Approach 2:
The single mask pattern is segmented into different regions: first mask regions for forming the gate line, second mask regions for forming the pillar-shaped semiconductor layer, and third mask regions for forming the planar silicon layer. This segmentation allows one mask to perform the functions of multiple masks while maintaining precise control over each component's formation.
2Productivity
If metal gate process is integrated with high-temperature process, then production efficiency is improved, but process integration becomes more difficult
Solution Approach 1:
The gate line and pillar-shaped semiconductor layer are formed in advance using the first etching step before the metal gate formation process. This preliminary formation allows subsequent metal gate deposition and high-temperature processing to proceed without interfering with the gate line structure, facilitating smooth process integration while maintaining high productivity.
3Object-affected harmful factors
If first insulating film is formed around fin-shaped semiconductor layer and etched back, then parasitic capacitance between gate line and substrate is reduced, but additional manufacturing steps are required
Solution Approach 1:
The formation of the insulating film around the fin-shaped semiconductor layer is merged with the gate line formation process. The same insulating film that is deposited to reduce parasitic capacitance also serves as the layer from which the gate line is etched. This eliminates the need for separate insulating film deposition and etching steps, reducing the total number of manufacturing steps while maintaining the parasitic capacitance reduction benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the number of required steps and eliminates misalignment between the pillar-shaped semiconductor layer and the gate line, enabling the easy production of metal gate SGTs while maintaining the integration of a metal gate process and high-temperature process, and provides adequate insulation for the gate electrode and line.
Implementation Method 1
depositing a first polysilicon on the second insulating film to conduct planarization
Implementation Method 2
etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate
Implementation Method 3
integrates a metal gate process and a high-temperature process
Data Source
AI summary
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.