Gate-Last Vertical Transistor Process for Thermal Budget Management
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Solution Overview
Problem
Conventional gate-first processes for forming vertical transport field-effect transistors face thermal budget restrictions, making it difficult to achieve high dopant activation and selective epitaxial growth of top source/drain regions, which limits device scaling and performance.
Innovation Solution
The implementation of gate-last processes, where top source/drain regions are formed prior to the final gate stack, allowing for selective doped epitaxial growth and activation anneal without thermal constraints, and the formation of a gate stack with a box profile between fins using a high-k dielectric, work function metal, and gate conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-first processes are used for forming vertical transport field-effect transistors, then the gate stack is formed early in the process, but thermal budget restrictions prevent high dopant activation and selective epitaxial growth of top source/drain regions
Solution Approach 1:
The patent inverts the conventional gate-first sequence by implementing a gate-last process where the gate stack is formed after the top source/drain regions. This inversion allows high-temperature processing steps for dopant activation and selective epitaxial growth to be performed before gate formation, eliminating thermal budget restrictions that would otherwise prevent achieving high dopant activation and controlled epitaxial growth.
Solution Approach 2:
The patent performs preliminary formation of top source/drain regions with dopant activation and selective epitaxial growth before forming the gate stack. By completing these thermally-intensive operations in advance, the process enables high dopant activation and controlled epitaxial growth without the thermal budget constraints that would exist if the gate were formed first.
2Productivity
If conventional gate-first processes are used, then processing sequence is simple, but device scaling and performance are limited due to thermal constraints
Solution Approach 1:
The patent inverts the conventional processing sequence by forming the gate stack after the top source/drain regions rather than before. This inversion enables advanced device scaling and high-performance characteristics by allowing thermally-intensive processing steps to occur without gate interference, despite increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved dopant activation and epitaxial growth of top source/drain regions, overcoming thermal budget limitations and enabling scalable and high-performance vertical transport field-effect transistors with a box profile gate stack.
Implementation Method 1
a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack comprising a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer
Implementation Method 2
a work function metal layer formed over the gate dielectric
Data Source
AI summary
A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.