Gate Last Vertical FET Self-Aligned Spacers
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Solution Overview
Problem
The challenge in forming vertical field effect transistor (VFET) devices lies in implementing a replacement metal gate (RMG) process flow, which is complicated by the vertical orientation of VFETs, particularly due to the susceptibility of high-κ dielectrics to high temperature damage during source and drain formation.
Innovation Solution
The technique involves forming a stack with doped source and drain regions, sacrificial layers of silicon germanium (SiGe) with specific germanium content, patterning trenches, filling with epitaxial silicon channel material, selectively removing sacrificial layers to form cavities, and annealing to diffuse dopants, ultimately creating self-aligned replacement metal gates and spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a replacement metal gate (RMG) process flow is employed for VFET fabrication, then the metal gate materials are protected from high temperature damage, but the vertical orientation of VFETs complicates the process implementation
Solution Approach 1:
The patent divides the gate formation process into distinct stages: forming sacrificial dummy gates, completing source/drain regions, removing sacrificial gates, and forming replacement metal gates. This segmentation allows each step to be optimized independently, protecting the metal gate from high temperature damage while managing process complexity through systematic breakdown of operations.
Solution Approach 2:
The patent employs preliminary formation of sacrificial dummy gates and high-κ dielectric layers before metal gate deposition. This preliminary action establishes the gate structure in advance, allowing subsequent metal gate replacement without exposing the metal to high temperature processing, thus protecting material integrity while streamlining the overall process.
2Reliability
If high-κ dielectrics are employed with metal gate stacks, then device performance is improved, but the dielectrics are susceptible to high temperature damage during source and drain formation
Solution Approach 1:
The high-κ dielectric layer is formed as part of the gate stack structure before metal gate deposition and before high temperature source/drain processing. This preliminary formation protects the dielectric from subsequent high temperature damage while maintaining its performance benefits in the final device structure.
Solution Approach 2:
The patent uses sacrificial dummy gates as intermediary structures that occupy the gate region during high temperature source/drain formation. These intermediaries shield the high-κ dielectric from direct high temperature exposure, preventing damage while allowing the dielectric to maintain its performance-enhancing properties in the final device.
3Manufacturing precision
If self-aligned spacers and junctions are formed, then manufacturing precision is improved, but the process steps increase
Solution Approach 1:
The patent employs self-aligned spacer formation where spacers are deposited conformally on patterned structures and then etched back to create precisely aligned features. The existing structures serve as their own alignment references, eliminating the need for separate alignment steps and achieving high manufacturing precision without proportionally increasing process complexity.
Solution Approach 2:
The patent combines multiple functions into integrated process steps, such as forming spacers that simultaneously serve as alignment references and structural elements, and creating junctions that are self-aligned to gate regions. This merging reduces the number of discrete steps needed while maintaining high precision through combined operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the successful formation of gate last VFET devices with self-aligned spacers and junctions, effectively addressing the challenges of high temperature sensitivity and achieving a robust RMG process for VFET fabrication.
Implementation Method 1
annealing the stack to diffuse dopants from the doped bottom source and drain and the doped top source and drain into the channel material between adjacent gate regions, forming bottom source and drain extensions and top source and drain extensions
Data Source
AI summary
Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.