Gate Layer Segmentation for ONO Stack Fabrication

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Solution Overview

Problem

The performance of flash memory devices is largely affected by the design of their gate active area, necessitating a modification of the memory architecture to enhance overall device performance.

Innovation Solution

A method involving the formation of a semiconductor device with a substrate, first and second gate structures, shallow trench isolation, and an oxide-nitride-oxide stack, where the gate layer is partially removed and spacers are used to define the gate structures without additional photomasks, allowing for improved performance by reducing the active area of the gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate layer is kept as a single continuous structure, then the manufacturing process is simpler, but the device performance is limited due to large active area

Engineering Contradiction:

Improvegate structure precisionVSAvoidgate structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate layer is divided into multiple segments by introducing gate spacers that define first and second gate structures. This segmentation reduces the active area of the gate while maintaining manufacturing feasibility through standardized spacer formation processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Gate spacers are introduced as intermediary structures to define the gate structures. These spacers act as masks during etching processes, enabling precise definition of gate regions without requiring additional photomask steps.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If additional photomasks are used to define gate structures, then the gate active area can be reduced, but the manufacturing complexity and cost increase

Engineering Contradiction:

Improvegate active area definitionVSAvoidfabrication process simplicity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The gate spacers serve dual purposes: they define the gate structures and act as self-aligned masks for subsequent etching steps. This self-service approach eliminates the need for additional photomask alignment steps while maintaining precise gate active area definition.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The gate spacers perform multiple functions simultaneously: they define gate regions, serve as etch masks, and establish alignment references for subsequent processing steps. This multi-functionality reduces the overall number of fabrication steps required.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9620368B2Method for fabricating non-volatile memory with ONO stack

Publication Date: 2017.04.11 POWERCHIP SEMICON MFG CORP

AI summary

A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.