Gate Structure Layout for Lower Contact Resistance in Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices, poor contact between the gate structure and the source/drain layer leads to increased contact resistance and inefficient signal transfer, affecting the integration and performance of logic devices.
Innovation Solution
The semiconductor device design includes gate structures with varying insulation thicknesses and electrode widths, where the first gate structure has a thinner insulation layer compared to the second and third gate structures, allowing for improved contact plug integration and enhanced voltage application across different regions, thereby ensuring effective signal transfer and reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure and source/drain layer are connected to contact plug structure, then electrical signals can be transferred, but contact resistance increases due to poor contact
Solution Approach 1:
The patent applies different gate insulation thicknesses to different gate structures based on their specific requirements. The first gate structure has a thinner gate insulation layer to reduce contact resistance and improve contact quality with the contact plug structure, while the second gate structure has a thicker gate insulation layer for other performance requirements. This local differentiation resolves the contradiction by optimizing each region's properties according to its specific needs.
Solution Approach 2:
The patent changes the gate insulation thickness parameter to resolve the contact resistance issue. By reducing the gate insulation thickness in the first gate structure, the electrical contact resistance between the gate structure, source/drain layer, and contact plug structure is reduced, thereby improving contact quality and signal transfer efficiency.
2Productivity
If gate structures with different insulation thicknesses are used, then signal transfer efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the gate structures into different types (first gate structure and second gate structure) with different gate insulation thicknesses. This segmentation allows each gate structure to be optimized for its specific function, improving overall signal transfer efficiency while managing complexity through systematic classification and differentiation of gate structure types.
Data Source
AI summary
A semiconductor device includes a bulk substrate including a first region and a second region, a buried oxide layer and a semiconductor layer stacked on the first region, a first gate structure disposed on the semiconductor layer, a first source/drain layer disposed at an upper portion of the semiconductor layer adjacent to the first gate structure, a second gate structure disposed on the second region, and a second source/drain layer disposed at an upper portion of the bulk substrate adjacent to the second gate structure.