Region-Specific Gate Structure Layout for Semiconductor Leakage
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Solution Overview
Problem
As semiconductor devices become smaller to increase storage capability, they face issues with leakage due to increased integration levels.
Innovation Solution
The semiconductor device incorporates a first gate structure with a curved bottom surface and a second gate structure with a flat bottom surface, both supported by a substrate, where the first gate structure's bottom surface is curved and the second gate structure's bottom surface is coplanar with the substrate's top surface, enhancing the device's structural integrity and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory cells are integrated to increase storage capability, then storage capability is improved, but leakage issue worsens
Solution Approach 1:
The patent applies different gate structure configurations to different regions of the semiconductor device. Specifically, the peripheral region contains gate structures with curved bottom surfaces that extend below the substrate top surface, while the active region has gate structures with coplanar bottom surfaces. This local differentiation allows the peripheral region to better contain leakage currents without affecting the memory cell performance in the active region, thus resolving the contradiction between increased integration and leakage control.
2Productivity
If device size is reduced to increase integration level, then integration level is improved, but leakage issue worsens
Solution Approach 1:
The patent implements local quality by creating region-specific gate structures. The peripheral region gate structures have curved bottom surfaces extending below the substrate, forming a deeper containment well for leakage currents. This localized structural modification enables high integration density while maintaining reliability by addressing leakage at its source in the peripheral region without compromising the compact design.
3Reliability
If gate structure bottom surface is curved and below substrate top surface, then leakage is reduced, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by applying the curved bottom surface gate structure only to the peripheral region, while keeping the active region gate structures simple and coplanar. This selective approach contains the complexity where it is most needed for leakage control, while maintaining simplicity in the memory cell regions, thus achieving leakage reduction without excessive overall device complexity.
Solution Approach 2:
The patent segments the gate structures into two distinct types: those with curved bottom surfaces for the peripheral region and those with coplanar bottom surfaces for the active region. This segmentation allows each type to be optimized for its specific function - leakage containment in periphery and memory operation in active region - reducing the complexity burden on the overall device.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, a word line structure, a first gate structure, and a second gate structure. The substrate has an active region and a peripheral region surrounding the active region. The word line structure is disposed in the active region of the substrate. The first gate structure is disposed in the peripheral region of the substrate, wherein a bottom surface of the first gate structure is curved toward the substrate, and the bottom surface of the first gate structure is below a top surface of the substrate. The second gate structure is disposed in the peripheral region of the substrate and the second gate structure located between the word line structure and the first gate structure, wherein a bottom surface of the second gate structure is coplanar with the top surface of the substrate.