Gate Structure Layout Patterns for Sub-Resolution Lithography
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Solution Overview
Problem
The challenge in integrated circuit (IC) fabrication is to achieve a higher gate density while minimizing the cost, which is hindered by the limitations of existing lithographic technologies, particularly in forming masks with pitches smaller than the spatial resolution, leading to increased costs and reduced transistor performance due to current leakage.
Innovation Solution
The method involves creating a layout design with gate structure layout patterns having a pitch smaller than the spatial resolution of the lithographic technology, allowing for multiple-patterning processes and the use of mask layout layers with specific pattern widths and gaps to adjust threshold voltages and reduce leakage current through dummy transistors, thereby optimizing IC fabrication costs and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lithographic technology is used to form masks with pitches smaller than spatial resolution, then gate density is improved, but manufacturing cost increases and manufacturing precision deteriorates
Solution Approach 1:
The mask formation process is segmented into multiple steps (multiple-patterning) to achieve fine pitch features that cannot be formed in a single lithographic step. This divides the complex task of forming sub-resolution features into manageable sequential operations, enabling high gate density while using existing lithography tools.
Solution Approach 2:
Mandrel structures are formed in advance before the final mask pattern is created. These preliminary mandrels serve as templates for subsequent patterning steps, allowing the lithographic tool to work at its native resolution while still achieving finer final features through the multi-step process.
2Productivity
If lithographic technology is used to form masks with pitches smaller than spatial resolution, then gate density is improved, but manufacturing precision deteriorates
Solution Approach 1:
The pattern formation is segmented into multiple precise steps where each step operates within the lithographic resolution limits. By breaking down the complex sub-resolution patterning into sequential operations with intermediate structures, each step maintains manufacturing precision while the cumulative result achieves the desired fine pitch.
Solution Approach 2:
Mandrel structures serve as intermediary elements that bridge the gap between lithographic resolution capabilities and the desired finer final pattern. These intermediaries enable the transfer of patterns at a resolution level below the native capability of the lithographic tool.
3Object-generated harmful factors
If dummy transistors are used at cell boundaries, then current leakage is reduced, but device complexity increases
Solution Approach 1:
Different transistor structures are applied locally based on position: functional transistors in critical paths maintain original design, while dummy transistors at cell boundaries are specifically modified with adjusted gate structures. This localized differentiation reduces leakage where needed without unnecessarily complicating the entire device.
Solution Approach 2:
The gate structure parameters (such as gate length or width) are changed specifically for dummy transistors to adjust their threshold voltages and reduce leakage current. This parameter adjustment allows the dummy transistors to perform their leakage-blocking function while maintaining a relatively simple overall structure.
Data Source
AI summary
A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.