Gate Lead-Out Lines for Narrow Display Frames
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Solution Overview
Problem
Existing display devices face challenges in narrowing the frame region without reducing the pixel aperture ratio, leading to display unevenness and decreased quality due to higher resistance in gate signal lines.
Innovation Solution
A display device configuration where gate lines and source lines are arranged with overlapping gate lead-out lines, each gate line connected to multiple lead-out lines, and insulating films are used to equalize resistance, ensuring the frame can be narrowed without compromising pixel aperture ratio or display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the width of the lead-out gate signal line is set smaller than the width of the source signal line to prevent reduction in pixel aperture ratio, then the pixel aperture ratio is maintained, but the resistance to the gate signal in the lead-out gate signal line becomes larger than the resistance in the gate signal line, causing display unevenness and reduced display quality
Solution Approach 1:
The gate signal transmission path is segmented into multiple lead-out gate signal lines (GD1-GDn) that are distributed across different layers. Each lead-out line connects to the gate driver at different positions, dividing the single high-resistance path into multiple parallel paths, thereby reducing overall resistance while maintaining pixel aperture ratio.
Solution Approach 2:
The patent transitions from a single-layer wiring structure to a multi-layer wiring structure. Lead-out gate signal lines are formed in different layers (first through fourth insulating film layers), utilizing the vertical dimension to route multiple signal paths without increasing the horizontal footprint, thus reducing resistance without compromising pixel aperture ratio.
2Area of stationary object
If gate lead-out lines are arranged to overlap with source signal lines to narrow the frame, then the frame region is reduced, but the resistance in the gate signal transmission path increases, causing display unevenness
Solution Approach 1:
The patent utilizes multiple wiring layers to route gate lead-out lines and source signal lines in different vertical planes. This allows the lines to overlap in the planar view (narrowing the frame) while maintaining separate physical paths in three-dimensional space, preventing unwanted electrical interactions and maintaining signal integrity.
Solution Approach 2:
Insulating films (first through fourth) serve as intermediaries between gate lead-out lines and source signal lines that overlap in planar view. These insulating layers electrically isolate the two signal types while allowing them to share the same physical space, enabling frame narrowing without signal interference or increased resistance.
3Reliability
If multiple gate lead-out lines are electrically connected to a single gate line at different positions, then the overall resistance of the gate signal transmission path is reduced, but the device complexity increases
Solution Approach 1:
The gate signal transmission system is segmented into multiple standardized lead-out line units, each following the same structural pattern (insulating film sequence + conductive line). This modular segmentation reduces complexity by repeating a proven design pattern rather than creating unique wiring solutions for each connection point.
Solution Approach 2:
The multi-layer insulating film structure and lead-out line configuration serve multiple functions simultaneously: they provide electrical isolation between gate and source signals, reduce transmission resistance through parallel paths, enable frame narrowing via overlapping arrangements, and maintain pixel aperture ratio. This universal structure handles multiple requirements without proportionally increasing complexity.
Data Source
AI summary
Provided is a display device, including: a plurality of gate lines extending in a first direction; a plurality of source lines extending in a second direction; a gate driver configured to output a gate signal; and a plurality of gate lead-out lines extending in the second direction and being configured to transmit the gate signal to the plurality of gate lines, in which each of the plurality of gate lines is electrically connected to at least one of the plurality of gate lead-out lines, and at least one of the plurality of gate lines is electrically connected to at least two of the plurality of gate lead-out lines.