Gate Lead Line Routing for Narrow Bezel Display Signal Delay
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Solution Overview
Problem
In narrow bezel display technology, the long length of gate lead lines causes a delay in driving thin film transistors due to a delay of gate signals from the gate driver.
Innovation Solution
The display device incorporates gate signal lines and data signal lines extending in different directions, with gate lead lines connecting to gate signal lines in the same direction as data signal lines, and strategically placing one gate lead line between neighboring data signal lines to reduce capacitance between gate signal lines and the common electrode, thereby minimizing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate lead lines are extended to connect gate drivers to gate signal lines in narrow bezel configuration, then the bezel width is reduced, but the signal delay increases due to long gate lead line length
Solution Approach 1:
The gate lead lines are segmented into multiple sections with different routing paths. Some gate lead lines are routed between data signal lines while others are routed outside, dividing the single long path into multiple shorter segments that can be optimized independently for signal timing
Solution Approach 2:
The gate lead lines are routed in three-dimensional space by utilizing the space between data signal lines (vertical dimension) in addition to the horizontal plane, effectively reducing the path length without increasing bezel width
2Reliability
If gate lead lines are routed between data signal lines, then capacitance between gate signal lines and common electrode is reduced, but manufacturing complexity increases
Solution Approach 1:
The gate lead lines are divided into first gate lead lines routed between data signal lines and second gate lead lines routed outside, allowing selective optimization of signal timing for critical paths while maintaining manufacturability for less critical connections
Solution Approach 2:
Different routing strategies are applied to different gate lead lines based on their specific signal timing requirements. Gate lead lines connecting to gate signal lines that require faster timing are routed between data signal lines, while others use external routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal delay by minimizing capacitance between gate signal lines and the common electrode, improving the timing of driving thin film transistors.
Implementation Method 1
one of the plurality of gate lead lines is disposed between two neighboring data signal lines among the plurality of data signal lines... reduces capacitance between gate signal lines and the common electrode
Data Source
AI summary
A display device includes: gate signal lines extending in a first direction; data signal lines extending in a second direction; gate lead lines extending in the second direction and respectively connected to the gate signal lines; pixel electrodes electrically connected to the data signal lines, respectively; and a common electrode opposed to the plurality of pixel electrode. Each one of gate lead lines is disposed between two neighboring ones of the data signal lines. A first opening is provided for a first area of the common electrode, and the first area overlaps one of the gate signal lines, and is between the one of the gate lead lines and a one of the two neighboring data signal lines that is closer to the one of the gate lead lines than is the other one of the two neighboring data signal lines.