Gate Length Bias and High Threshold Voltage Cell Replacement for Leakage Power
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Solution Overview
Problem
The semiconductor device industry faces challenges in reducing leakage power, particularly due to sub-threshold leakage current, which increases with the number of devices on a chip, and existing optimization techniques either compromise speed or increase manufacturing costs by using different threshold voltage gates.
Innovation Solution
The method involves selectively replacing non-critical instances of chip blocks with gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells based on activity factors and slack thresholds, minimizing performance impact and reducing power consumption without additional manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If threshold voltage is reduced to improve speed, then device speed is improved, but leakage current increases
Solution Approach 1:
The patent applies local quality by differentiating threshold voltage settings at the instance level rather than uniformly across the entire circuit. Critical path instances maintain low threshold voltage for speed, while non-critical path instances use high threshold voltage to reduce leakage. This localized differentiation resolves the contradiction by optimizing each region's threshold voltage according to its specific performance requirements.
Solution Approach 2:
The patent segments the circuit into critical and non-critical paths, and further segments instances within these paths based on activity factors and slack thresholds. This segmentation enables selective application of different threshold voltage configurations, allowing speed optimization on critical paths while minimizing leakage on non-critical paths, thereby resolving the speed-leakage tradeoff.
2Loss of energy
If high threshold voltage gates are used to reduce leakage, then leakage power is reduced, but circuit speed decreases
Solution Approach 1:
The patent implements local quality by assigning high threshold voltage specifically to non-critical path instances with low activity factors and high slack, rather than uniformly across all instances. This localized application ensures leakage reduction occurs only where it does not impact critical timing paths, resolving the contradiction between leakage reduction and speed maintenance.
Solution Approach 2:
The patent introduces dynamic decision-making based on activity factors and slack thresholds to determine threshold voltage assignment. Instances are dynamically evaluated against these parameters, and high threshold voltage is applied conditionally only when it does not violate timing constraints. This dynamic approach resolves the contradiction by adapting threshold voltage selection to actual circuit operating conditions.
3Loss of energy
If different threshold voltage gates are used to optimize performance and power, then power consumption is optimized, but manufacturing cost increases due to extra masks and lithography steps
Solution Approach 1:
The patent achieves universality by using a single standard cell library that can operate in multiple threshold voltage modes (low and high) through selective instance replacement. Rather than requiring separate cell libraries for different threshold voltages, the method uses activity factor and slack-based selection to determine which instances should use high threshold voltage, eliminating the need for additional masks and lithography steps while still optimizing power consumption.
4Loss of energy
If more instances are replaced with high threshold voltage cells to reduce power, then power consumption is reduced, but timing constraints may be violated
Solution Approach 1:
The patent applies preliminary action by pre-calculating activity factors and slack thresholds for all instances before performing replacement. Instances are evaluated against these pre-computed parameters to determine eligibility for high threshold voltage replacement. This preliminary evaluation ensures that only instances with sufficient timing margin are replaced, preventing timing constraint violations while maximizing power reduction opportunities.
Solution Approach 2:
The patent implements feedback by using slack threshold as a dynamic criterion for replacement eligibility. Instances are monitored against their slack thresholds, and replacement decisions are made based on whether the instance can tolerate the performance impact of high threshold voltage without violating timing constraints. This feedback mechanism ensures timing reliability is maintained while achieving power optimization.
Data Source
AI summary
Broadly speaking, the embodiments of the present invention fill the need for a method of designing semiconductor device chips with reduced power consumption. The embodiments describe methods that are activity-based and are used for power optimization. The embodiments provide methods of selecting instances of a block of a chip to be replaced by either gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells with minimal impact (little or no impact) on the overall performance of the chip. Only instances not on the critical path(s) are selected. Instances with low activities and high slack thresholds are chosen to be replaced by either GBIAS cells or HVT cells. By replacing the instances with low activities and high slack threshold, the performance impact on the block and chip is minimized. The replacement results in net power reduction, which is critical to advanced device technologies.