Gate Length Control via Carbon-Enriched Width-Setting Patterns
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Solution Overview
Problem
In the context of down-scaled semiconductor devices, maintaining a constant gate length is crucial to prevent leakage currents and ensure desired performance, but existing technologies struggle to achieve this due to variations in transistor size and structure.
Innovation Solution
The integration of width-setting patterns with a higher carbon content than the insulating spacer, which define the width of the gate structure space, ensures a constant gate length by maintaining the width of the space for the gate electrode layer, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor size is reduced for down-scaling, then the device density and integration capability are improved, but the gate length becomes difficult to maintain constant leading to increased leakage currents and performance degradation
Solution Approach 1:
The patent divides the gate structure formation process into multiple stages using different patterns (first and second width-setting patterns) and materials (mandrel layer, spacer layer, insulating layer). This segmentation allows independent control of gate length and width parameters, enabling constant gate length maintenance even as overall device size is reduced for higher density.
Solution Approach 2:
The patent introduces intermediate layers (mandrel layer with carbon-containing material, spacer layer, and insulating layer) that act as mediators to define and control the gate structure dimensions. These intermediary layers enable precise gate length control by serving as templates and boundaries during the formation process, decoupling gate length from overall device scaling.
2Shape
If the gate length is reduced to maintain constant dimensions in down-scaled devices, then the transistor size is optimized, but leakage currents increase and desired performance is not achieved
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the gate structure. The mandrel layer uses carbon-containing material with specific etch selectivity, while the spacer and insulating layers have different dielectric properties. This local differentiation allows the gate length to be independently optimized for leakage suppression while the overall transistor size is reduced for performance optimization.
3Manufacturing precision
If complex width-setting patterns with different carbon contents are introduced to maintain constant gate length, then the gate length control is improved, but the device complexity and fabrication process complexity increase
Solution Approach 1:
The patent controls the carbon content parameter in the mandrel layer (greater than 5 atom%, preferably 10-30 atom%) to achieve specific etch selectivity and structural stability. By precisely controlling this material parameter, the complex multi-layer structure achieves reliable gate length definition without requiring even more complex fabrication processes. The carbon content parameter becomes a key control variable that simplifies the overall process control.
Data Source
AI summary
An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.