Gate-Level Substitution for Testing Analog Dynamic Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional digital testing tools are inadequate for testing analog dynamic circuits due to their representation at the transistor level, which prevents effective generation of test patterns for internal nodes, resulting in low test coverage.

Innovation Solution

The method involves designing equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit, converting it to a gate-level substitution circuit, and importing it into a digital testing tool to generate and apply test patterns, thereby increasing test coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the analog dynamic circuit is represented at the transistor level, then the circuit operates at faster speed and lower energy consumption, but the digital testing tool cannot generate test patterns for internal nodes, resulting in low test coverage

Engineering Contradiction:
Improvecircuit operating speedVSAvoidtest coverage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent creates a gate-level substitution circuit that copies the functional behavior of the transistor-level dynamic circuit using static logic gates. This substitution circuit serves as a testable model that preserves the original circuit's logic functionality while being compatible with digital testing tools, thereby enabling comprehensive test pattern generation without modifying the actual high-speed dynamic circuit

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The gate-level substitution circuit acts as an intermediary between the transistor-level dynamic circuit and the digital testing tool. It translates the analog dynamic circuit's behavior into a form that digital testing tools can process, allowing test patterns to be generated for internal nodes without directly interfacing with the transistor-level circuit

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the analog dynamic circuit is converted to gate-level representation, then test coverage is improved, but the circuit complexity increases due to substitution of dynamic logic elements

Engineering Contradiction:
Improvetest coverageVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the dynamic circuit into individual dynamic logic elements (such as dynamic gates), replaces each with equivalent static gate-level models, and then integrates them into a complete gate-level substitution circuit. This segmented approach makes the conversion process systematic and manageable, though it does increase the overall gate count

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If the transistor-level analog dynamic circuit is directly tested with digital testing tool, then the testing process is simple, but the test pattern generation is inadequate for internal nodes

Engineering Contradiction:
Improvetesting process simplicityVSAvoidtest pattern effectiveness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

Instead of directly testing the transistor-level circuit, the patent creates a gate-level substitution circuit that copies the logical functionality. This substitution circuit can be imported into standard digital testing tools like ATPG, maintaining ease of operation while significantly improving test pattern effectiveness for internal nodes

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11144697B1Processing method for applying analog dynamic circuit to digital testing tool
Publication Date: 2021.10.12 RDC SEMICON CO LTD
  • US11144697B1 patent drawing
  • US11144697B1 patent drawing
  • US11144697B1 patent drawing

AI summary

A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.