Gate-Level Leakage Current Geometry Data Estimation
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Solution Overview
Problem
Current methods for estimating static leakage power in integrated circuits are inefficient and time-consuming, often requiring several days to complete, even for circuits with millions of gates, and lack accuracy compared to cell-based techniques.
Innovation Solution
A gate-level approach is introduced that generates cell-level leakage current geometry data, which is then used to determine gate-level leakage current geometry data independently of process, voltage, and temperature (PVT) corners, allowing for efficient static leakage power estimation by aggregating data and reducing the number of multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional cell-based techniques are used for static leakage power estimation, then measurement precision is improved, but productivity deteriorates due to several days of computation time
Solution Approach 1:
The patent segments the computation process by separating geometry data extraction (performed once during design phase) from leakage current calculation (performed during operation). The gate-level netlist is processed to extract geometry data for each gate, which is then stored and reused for multiple leakage calculations under different operating conditions, avoiding repeated full-circuit simulations.
Solution Approach 2:
The patent performs preliminary extraction of leakage current geometry data from the gate-level netlist during the design phase, before actual leakage power estimation is needed. This geometry data includes transistor dimensions, positions, and connectivity information that remain constant across different operating conditions, enabling rapid recalibration without re-running time-consuming simulations.
2Measurement precision
If conventional cell-based techniques are used for static leakage power estimation, then measurement precision is improved, but device complexity increases due to detailed cell-level analysis requirements
Solution Approach 1:
The patent introduces an intermediary data structure - the extracted geometry data from gate-level netlist - that bridges the gap between detailed cell-level specifications and simplified estimation requirements. This geometry data serves as a mediator that captures essential leakage characteristics without requiring access to or processing of complete cell-level transistor details during operation.
Solution Approach 2:
The patent creates simplified copies of cell leakage characteristics by extracting and storing geometry data that represents the essential leakage properties of each gate. Instead of using full cell-level transistor models, the system uses these extracted geometry copies that retain the necessary information for accurate leakage estimation while dramatically reducing computational complexity.
3Productivity
If gate-level approach with geometry data extraction is used, then productivity is improved with 10 minutes estimation time, but measurement precision may deteriorate compared to cell-based techniques
Solution Approach 1:
The patent changes the parameters used for leakage estimation from detailed cell-level transistor parameters to extracted geometry parameters from gate-level netlist. By focusing on essential geometric characteristics (transistor widths, lengths, areas) rather than complete device models, the system achieves rapid calculation while maintaining sufficient accuracy for most design purposes.
Solution Approach 2:
The patent applies local quality by extracting and using only the specific geometry data relevant to leakage current for each gate, rather than processing all cell-level details. This selective extraction focuses computational resources on the most critical parameters (channel width, length, area) that dominate leakage behavior, achieving good accuracy with reduced complexity.
Data Source
AI summary
Leakage current estimation for a circuit can include generating a cell leakage library including cell-level leakage current geometry data for different states of cells of a cell library, wherein the cells are specified as transistor-level netlists, and determining, using a processor, gate-level leakage current geometry data for gates of a gate-level netlist for the circuit based upon states of the gates for a selected operating state of the circuit and the cell-level leakage current geometry data. Total leakage current geometry data can be determined, using the processor, for the gate-level netlist by aggregating the gate-level leakage current geometry data.