Gate Level Logic Encryption with Integrated Key Transistors
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Solution Overview
Problem
The increasing reliance on third-party foundries for integrated circuit (IC) fabrication poses security and reliability concerns due to intellectual property theft, IC counterfeiting, and the potential insertion of hardware Trojans, with current logic encryption techniques resulting in high performance, power, and area overheads.
Innovation Solution
Implementing combinational logic encryption using XOR gates, look-up tables (LUTs), and transmission gate topologies to alter the IC's logic structure, requiring a key for correct operation, while reducing overhead through stack-based and transmission gate topologies that minimize power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic encryption is implemented using traditional methods (XOR gates or LUTs), then IC security is improved, but performance, power, and area overhead increase significantly
Solution Approach 1:
The patent transforms the encryption approach by changing the functional parameters of the gate itself. Instead of adding external encryption logic (XOR gates or LUTs), the invention modifies the internal parameters of standard gates (AND, OR, NAND, NOR) by introducing key-controlled transistors that alter the gate's logic function. This parameter change allows the gate to dynamically switch between encrypted and non-encrypted states, reducing overhead while maintaining security.
Solution Approach 2:
The patent creates universal encrypted gates that can perform multiple logic functions (AND, OR, NAND, NOR) depending on the key input values. By making the gates multi-functional through key control, the design eliminates the need for separate encryption circuits for different gate types, thereby reducing area and complexity overhead while providing comprehensive security across the entire logic network.
2Reliability
If more encrypted gates are placed in the circuit to enhance security, then protection against IP theft and hardware Trojans is improved, but area and power consumption increase
Solution Approach 1:
The patent merges the encryption function directly into the existing logic gates by sharing transistors and circuit resources. The key-controlled transistors are integrated within the gate structure itself, allowing the encryption functionality to be combined with the logic function in a single unified circuit element. This merging eliminates the need for separate encryption circuits, thereby reducing area overhead while providing comprehensive security coverage.
3Reliability
If traditional logic encryption methods are used, then security is improved, but performance overhead increases due to additional logic gates
Solution Approach 1:
The patent implements preliminary action by pre-configuring the gates with key-controlled transistors during the design phase. The encryption logic is built into the gate structure itself, so that when the circuit operates, the encryption function is already in place and active without requiring additional computation or external encryption circuits. This preliminary integration minimizes performance overhead by eliminating extra logic stages.
Data Source
AI summary
There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. One of the approaches provides a circuit having a gate topology comprising a logic gate with integrated key transistors, where the key transistors comprise at least a PMOS stack and an NMOS stack. The PMOS stack comprises a first PMOS switch and a second PMOS switch, where the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch. The NMOS stack comprises a first NMOS switch and a second NMOS switch, where the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch. Each of the above approaches may encrypt a circuit with certain advantages in delay and power consumption.