Gate-Level Masking Verification for Broken Intermediate Nets
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Solution Overview
Problem
Existing EDA tools may break masking during circuit design optimizations, rendering the final physical circuit vulnerable to side channel attacks, as they fail to maintain the integrity of masking after implementation.
Innovation Solution
Implement a post-implementation masking verification method using a gate level netlist to evaluate intermediate nets for broken masking by applying random values and checking if intermediate net values satisfy masking criteria, ensuring the circuit's security against side channel attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If EDA tools perform circuit design optimizations, then layout efficiency is improved, but masking integrity is broken
Solution Approach 1:
The verification process performs preliminary actions by checking masking integrity before the optimized circuit is deployed. The system proactively identifies masking violations during the design process rather than reactively fixing them after detection, allowing optimizations to be adjusted in advance to maintain both efficiency and security.
Solution Approach 2:
The system implements feedback mechanisms that continuously monitor masking integrity during circuit optimization. When masking violations are detected, the system provides feedback to the design process, enabling iterative adjustments to maintain both layout efficiency and masking correctness through coordinated optimization-verification cycles.
2Productivity
If EDA tools change operation order for optimization, then design efficiency is improved, but masking correctness is compromised
Solution Approach 1:
The verification system segments the circuit into functional blocks and tracks masking integrity at each segment level. This allows the system to identify which specific operations or blocks have compromised masking, enabling targeted corrections without requiring complete redesign of the entire circuit, thus preserving overall design efficiency.
Solution Approach 2:
The system monitors changes in operational parameters during optimization processes. When operation order changes are made for efficiency, the verification system tracks these parameter changes and detects when they result in masking violations, allowing corrective adjustments to maintain masking correctness while retaining optimization benefits.
3Measurement precision
If logical equivalence checking is used to verify circuits, then functional correctness is improved, but masking violations are undetected
Solution Approach 1:
The verification approach segments the verification process into multiple layers: functional equivalence checking at the circuit level and masking integrity verification at the intermediate net level. This segmentation allows the system to detect masking violations that would otherwise be hidden within functionally equivalent but insecure circuit implementations.
Solution Approach 2:
The system introduces intermediate verification steps that act as mediators between functional correctness verification and final circuit deployment. These intermediate checks specifically target masking integrity at critical points in the circuit, providing enhanced detection capability without completely overhauling the existing verification workflow.
Data Source
AI summary
A method for post-implementation masking verification of a source design of a circuit includes receiving a gate level netlist of a source design of a circuit having masking and evaluating intermediate nets of the netlist of the source design for a broken masking of an input. Evaluating intermediate nets of the netlist of the source design for broken masking of an input is performed for each implicit input associated with the input of the netlist of the source design of the circuit. For each implicit input, each of M random values for a share of each implicit input is applied as input to the netlist. When it is determined that the intermediate nets of the netlist do not satisfy a masking criteria using tracked intermediate net values, indicating that the intermediate net of the netlist is broken.