Gate-Level Netlist Simulation With Automated Probe Relocation

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Solution Overview

Problem

The manual debugging process of gate level netlists in integrated circuit simulations is time-consuming due to changes in wire connectivity and signal polarity caused by optimization, leading to inconsistencies in probing points and integrity issues in the development environment.

Innovation Solution

An automated system that uses a probe selection controller to identify and modify probing points in the gate level netlist, ensuring consistency across iterations by analyzing the RTL code and identifying alternative locations with lower probabilities of optimization changes, thereby reducing the need for manual intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual debugging is used to verify gate level netlists, then debugging accuracy can be maintained, but the debugging time increases significantly

Engineering Contradiction:
Improvedebugging accuracyVSAvoiddebugging time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs self-debugging by automatically detecting inconsistencies in probing points caused by optimization changes. The debugging circuitry autonomously identifies and flags issues without requiring manual intervention, allowing the design verification process to self-correct and reducing the time engineers spend on manual debugging while maintaining accuracy through automated consistency checks.

Inventive Principle:
Principle #25Self-service

2Productivity

If optimization is applied to gate level netlists, then circuit performance is improved, but wire connectivity and signal polarity inconsistencies occur

Engineering Contradiction:
Improvecircuit performanceVSAvoidprobing point consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The debugging circuitry implements a feedback mechanism that continuously monitors the gate level netlist for inconsistencies in wire connectivity and signal polarity after optimization. When optimization causes probing point changes, the feedback system detects these inconsistencies and flags them for correction, allowing the system to maintain reliability by automatically adapting to optimization-induced changes while preserving performance benefits.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If probing points are manually adjusted to account for optimization changes, then simulation accuracy is maintained, but the complexity of the verification process increases

Engineering Contradiction:
Improvesimulation accuracyVSAvoidverification process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The debugging circuitry automatically performs the task of adjusting probing points that would otherwise require manual intervention. By autonomously detecting inconsistencies and managing probing point adjustments, the system maintains simulation accuracy while eliminating the need for engineers to manually track and adjust probing points through multiple optimization iterations, thereby reducing verification process complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250291985A1Methods, systems, and apparatus to improve simulations of gate level netlists
Publication Date: 2025.09.18 TEXAS INSTRUMENTS INC
  • US20250291985A1 patent drawing
  • US20250291985A1 patent drawing
  • US20250291985A1 patent drawing

AI summary

Systems, apparatus, articles of manufacture, and methods are disclosed to improve simulations of gate level netlists. An example apparatus includes interface circuitry to obtain register transfer level code indicative of an operation of an integrated circuit, machine-readable instructions, and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to obtain a gate level netlist corresponding to the integrated circuit, the gate level netlist including modules in the integrated circuit and connections between the modules, obtain a first probe, the first probe representing a first location within the gate level netlist at which to monitor behavior, identify a root module that includes an output configured to determine a signal at the first location, and generate a second probe to replace the first probe representing a second location within the gate level netlist closer to the output of the root module than the first probe.