Gate-Level Netlist Timing Power Model for Digital Circuit Simulation
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Solution Overview
Problem
Current simulation-based power estimation methods for digital circuits are inefficient as they separate function verification and timing information acquisition, leading to inaccurate power estimation, particularly for glitch power, due to the use of static timing information only for critical paths.
Innovation Solution
Incorporating a timing and power model into the gate-level netlist of digital circuits to dynamically calculate transmission delays and power consumption, allowing for simultaneous function verification and power estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation-based power estimation method is used with SDF file, then power estimation can be performed, but the timing information is only for critical path not non-critical paths, leading to inaccurate power estimation
Solution Approach 1:
The patent transforms the static timing information stored in SDF files into dynamic timing information by introducing a timing model that calculates transmission delays in real-time during simulation based on actual signal waveforms and gate circuit characteristics. This allows timing information to adapt to different signal paths and conditions, providing accurate timing data for both critical and non-critical paths.
Solution Approach 2:
The patent changes the parameter representation from fixed SDF timing values to dynamic timing parameters calculated through the timing model. The timing model uses parameters such as gate delay characteristics, signal waveform properties, and path-specific conditions to compute accurate transmission delays for each signal path during simulation.
2Productivity
If function verification and timing information acquisition are performed separately, then each can be optimized independently, but the overall design efficiency is reduced
Solution Approach 1:
The patent merges function verification and power estimation processes by integrating the timing model directly into the simulation environment. This allows both function verification and timing-based power estimation to be performed simultaneously in a single simulation run, eliminating the need for separate processing steps and improving overall design efficiency.
Solution Approach 2:
The simulation system is enhanced with multi-functionality by incorporating the timing model that serves dual purposes: verifying circuit function through simulation and calculating power consumption through timing analysis. This unified approach allows the same simulation infrastructure to perform multiple tasks that were previously required separate dedicated processes.
3Measurement precision
If static timing analysis is used before simulation, then timing information can be prepared in advance, but the timing information cannot be acquired during simulation for accurate glitch power estimation
Solution Approach 1:
The patent prepares the timing model with pre-characterized gate circuit delay parameters and timing characteristics before simulation. This preliminary preparation allows the model to quickly calculate accurate timing information during simulation without adding significant computational overhead, enabling real-time timing analysis for glitch power estimation.
Solution Approach 2:
The timing model continuously receives feedback from the simulation process, including actual signal waveforms, switching activities, and circuit state information. This feedback mechanism allows the timing model to dynamically adjust and calculate accurate transmission delays for each signal path during simulation, enabling precise glitch power estimation that reflects actual circuit behavior.
Data Source
AI summary
The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.