Gate-Level Logic Simulation Accelerating Real X Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate-level logic simulation methods are inefficient in quickly determining whether Boolean functions represent real Xs, leading to time-consuming formal analysis and prolonged runtime, especially when encountering the same subcircuits multiple times during verification processes.
Innovation Solution
The method employs And-Inverter-Graph (AIG) representation of Boolean functions, using structure-based hash numbers to look up and apply pre-generated vectors for simulation, thereby skipping unnecessary formal analysis and accelerating real X detection by leveraging a vector database for repeated subcircuit analyses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If random simulation is used to determine if subckt output is non-constant, then detection speed is improved, but detection accuracy deteriorates because random patterns have very small probability of hitting special patterns
Solution Approach 1:
The patent pre-generates special test patterns (vectors) that are guaranteed to reveal real X conditions. These patterns are created in advance and stored for later use, eliminating the need to rely on random patterns during actual detection. The pre-computed patterns ensure that when a real X exists, it will be detected with high probability.
Solution Approach 2:
The patent creates a vector database that stores copies of proven test patterns for various subcircuits. When the same subcircuit is encountered again during verification, these pre-stored pattern copies are reused instead of generating new random patterns, maintaining both speed and accuracy consistently across multiple detections.
2Measurement precision
If formal Boolean analysis is performed to check whether output is constant, then detection accuracy is improved, but runtime increases because Boolean solver is time consuming
Solution Approach 1:
The patent applies a two-stage detection approach: first uses fast pattern-based simulation to check for real X conditions, and only performs time-consuming formal Boolean analysis when the pattern-based method is inconclusive. This partial application of formal analysis reduces overall runtime while maintaining accuracy for the majority of cases.
Solution Approach 2:
The patent uses inexpensive, quickly-generated test patterns as the primary detection mechanism. These patterns are computationally cheap to apply and can be executed rapidly, serving as a disposable first-line defense that filters out most cases without requiring expensive formal analysis.
3Reliability
If the same subckt is analyzed multiple times during verification, then verification thoroughness is improved, but total runtime increases because formal analysis must be repeated
Solution Approach 1:
The patent implements a vector database that stores analysis results and test patterns for previously analyzed subcircuits. When the same subcircuit is encountered again, the system copies and reuses the stored patterns and results instead of performing formal analysis again, maintaining verification thoroughness while dramatically reducing repeated computation time.
Solution Approach 2:
The patent performs analysis upfront and stores the results in a database before they are needed again. This preliminary action ensures that when the same subcircuit appears multiple times during verification, the work has already been done and can be quickly retrieved, eliminating redundant analysis.
Data Source
AI summary
A computer executable tool analyzes Boolean logic in a gate-level netlist with simulated values and efficiently determines whether a subset of the netlist produces real Xs or not. If whether the netlist produces real Xs or not cannot be quickly determined, further formal analysis needs to be performed, and this step can be time-consuming. By quickly determining whether real Xs are produced, the use of time-consuming formal methods can be reduced, thus reducing X-pessimism analysis time.