Gate-Level Logic Simulation Acceleration via Partition Boundary Analysis
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Solution Overview
Problem
Current coarse-grain multi-process parallel simulation methods for timing-accurate gate-level logic simulation face challenges such as timing information discrepancies at partition boundaries, unnecessary design/SDF file partitioning, and high communication overhead due to synchronization points, which hinder performance and practicality.
Innovation Solution
The solution preserves timing information by propagating value changes at gate terminals instead of port values, suppresses unneeded simulation workload by forcing constant values for unsimulated blocks, and determines whether synchronization points can be skipped based on flip-flop activity, eliminating the need for explicit design/SDF file partitioning and reducing communication overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If partition values are propagated at block boundaries using ports, then parallel simulation can be implemented, but timing information accuracy deteriorates because SDF delays describe delays between gate terminals not module ports
Solution Approach 1:
The patent introduces a delay compensation mechanism that acts as an intermediary between port-based partitioning and terminal-based timing. It calculates and applies compensation delays at partition boundaries to bridge the gap between port propagation and terminal-level timing accuracy, allowing both parallel simulation and precise timing measurement to coexist
Solution Approach 2:
The patent dynamically adjusts delay parameters at partition boundaries by calculating compensation values based on the difference between port delays and terminal delays. This parameter transformation allows the system to maintain timing accuracy while utilizing port-based partitioning for parallel simulation
2Productivity
If design and SDF file partitioning is performed explicitly, then parallel simulation can be implemented, but processing complexity increases due to extra partitioning steps and boundary delay handling
Solution Approach 1:
The patent extracts the timing compensation logic from the partitioning process itself. Instead of performing explicit design and SDF file partitioning, it separates the partitioning operation from the timing adjustment operation, applying delay compensation independently at partition boundaries to reduce overall process complexity
Solution Approach 2:
The patent creates a universal delay compensation mechanism that works across different partitioning schemes and design configurations. This multi-functional approach allows the same compensation logic to handle various partition boundary scenarios without requiring separate partitioning procedures
3Measurement precision
If synchronization points are established at all gate terminals, then timing accuracy is maintained, but communication overhead increases due to large number of events at each synchronization point
Solution Approach 1:
The patent applies different synchronization strategies to different locations in the circuit. Instead of uniform synchronization at all gate terminals, it implements selective synchronization only at critical partition boundaries and key signal paths, maintaining timing accuracy where needed while reducing overall communication overhead
Data Source
AI summary
A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.