Gate-Level Simulation X-Pessimism Correction
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Solution Overview
Problem
Gate-level logic simulation is hindered by false Xs generated due to X-pessimism from uninitialized latches and sequential cells, leading to inaccurate results and difficulty in distinguishing between bugs and actual Xs.
Innovation Solution
A computer-executable processing component analyzes fanout-cones of uninitialized latches and input, state, and output transitions of sequential cells to generate fixes, replacing false Xs with correct values, ensuring accurate simulation results by identifying and correcting false Xs in downstream logic and sequential cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-level logic simulation is performed with uninitialized latches and sequential cells, then simulation coverage and completeness are improved, but false Xs are generated due to X-pessimism leading to inaccurate results
Solution Approach 1:
The patent segments the simulation analysis into two distinct parts: (1) analyzing fanout-cones of uninitialized latches to identify false Xs, and (2) analyzing sequential cell transitions to distinguish real Xs from false Xs. This segmentation allows targeted fixes to be applied to specific sources of false Xs without affecting the entire simulation, thereby improving simulation accuracy while maintaining comprehensive coverage.
Solution Approach 2:
The patent performs preliminary analysis of latch fanout-cones and sequential cell transitions before the main simulation to identify potential false X sources. By pre-identifying uninitialized latches and analyzing their fanout-cones, the system can apply fixes in advance to eliminate false Xs before they corrupt simulation results, thereby improving reliability without losing simulation coverage.
2Measurement precision
If comprehensive analysis is performed to eliminate all false Xs, then simulation result accuracy is improved, but analysis time and computational resources increase
Solution Approach 1:
The patent applies local quality by focusing analysis resources on specific regions of the design that are most likely to generate false Xs. Instead of performing exhaustive analysis on the entire design, the system targets fanout-cones of uninitialized latches and sequential cells with X transitions, applying detailed analysis only where needed. This localized approach maintains high measurement precision while reducing overall analysis time.
Solution Approach 2:
The patent implements partial action by selectively analyzing only the necessary portions of the design - specifically fanout-cones of uninitialized latches and sequential cells with X transitions. Rather than performing complete exhaustive analysis on all circuit elements, the system applies analysis only to regions where false Xs are likely to occur, achieving sufficient accuracy without the full time cost of comprehensive analysis.
3Reliability
If sequential cells are modeled conservatively to handle X at clock pin, then robustness against unknown values is improved, but false Xs are generated at outputs corrupting downstream logic
Solution Approach 1:
The patent implements feedback by analyzing the actual transitions at sequential cell inputs and using this information to correct the conservative modeling behavior. The system monitors X transitions at clock and data inputs, then feeds this information back to determine whether output X corruption is justified or spurious. This feedback mechanism allows the system to maintain modeling robustness while eliminating false X propagation to downstream logic.
Solution Approach 2:
The patent introduces an intermediary analysis layer between the sequential cell model and downstream logic. This intermediary analyzes the actual transition behavior and acts as a mediator to prevent false Xs from propagating. By inserting this intermediate analysis step, the system maintains the robustness of conservative modeling while blocking the harmful propagation of false Xs to downstream circuit elements.
Data Source
AI summary
A computer executable processing component analyzes unknown (X) propagation from uninitialized latches in gate-level simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues. A computer executable processing component analyzes unknown (X) propagation from sequential cells in gate-level logic simulation and determines if the Xs cause false Xs to be generated due to X-pessimism. For Xs generated due to X-pessimism, simulation results are corrected and fixes are generated. Corrected simulation results match real hardware behavior and greatly reduces engineers' analysis effort on debugging X issues.