Gate-Level Logic Simulator Partitioning for Parallel Processing
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Solution Overview
Problem
Current logic simulators face significant performance limitations during the simulation of integrated circuit designs, particularly with large structural netlists, leading to poor design coverage, delayed product releases, and bugs that escape into silicon due to the time-consuming nature of gate-level netlist simulation.
Innovation Solution
The implementation of a logic simulator that selectively partitions and optimizes IC design descriptions for efficient simulation using multiprocessor architectures, leveraging massive parallelism through SIMD class processors and GP-GPUs, allowing for oblivious and event-driven simulation techniques to reduce computation time by simulating only necessary logic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional logic simulators are used to simulate gate-level netlists, then design verification can be performed, but simulation time becomes excessively long
Solution Approach 1:
The patent segments the gate-level netlist into multiple independent simulation domains or partitions, allowing parallel simulation across multiple processing units. Each partition can be simulated independently, enabling the simulator to process large netlists concurrently rather than sequentially, thus reducing overall simulation time while maintaining verification correctness
Solution Approach 2:
The patent transitions from single-processor sequential simulation to multi-processor parallel simulation architecture. By adding the dimension of parallel processing across multiple processors working simultaneously on different partitions of the netlist, the system achieves significant speedup in simulation time while preserving the accuracy of design verification
2Reliability
If simulation covers entire IC design, then design coverage is achieved, but computation time increases significantly
Solution Approach 1:
The patent implements selective simulation that focuses computational resources on critical paths and high-risk areas of the IC design rather than uniformly simulating every gate. By identifying and prioritizing simulation of logic components that have higher probability of containing bugs or design errors, the system achieves adequate design coverage with reduced computation time
Solution Approach 2:
The patent applies different simulation strategies to different regions of the IC design based on their characteristics. Critical modules with complex logic or high failure rates receive more thorough simulation attention, while simpler, lower-risk modules receive less intensive simulation. This localized approach optimizes the balance between design coverage and computational efficiency
Data Source
AI summary
Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.